Atrenta Confidential © 2008 Atrenta Inc.
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Checking Reset Tree
Reset_check02: Glitches in reset paths due to unexpected gates
(e.g. XOR gate in reset tree)
Reset_check04: Both positive and negative edges of
asynchronous reset used in a same design
Checking Clock-Reset race
Clock_Reset_check02: Race between flop output and its
clock/reset
Clock_Reset_info01: Clock and reset usage matrix for information
