RTL8316 芯片资料

所需积分/C币:38 2014-07-01 15:52:32 416KB PDF
收藏 收藏
举报

The RTL8316 supports IEEE 802.3x full duplex flow control and half duplex back pressure control. The ability of IEEE 802.3x flow control is auto-negotiated by writing the flow control ability via MDIO. For half duplex, the RTL8316 adopts a special back pressure design to allow forwarding of one pack
S REALTEK RTL8316 The rtl83 16 supports IEEE 802.3x full duplex flow control and half duplex back pressure control. The ability of iEee 802.3x flow control is auto-negotiated by writing the flow control ability via MDIO. For half duplex, the rtl8316 adopts a cial back pressure design to allow forwarding of one packet successfully after 48 force collisions. This back pressure algorithm can prevent the connected repeater from being partitioned due to excessive collisions. The full half duplex flow control ability can be enabled or disabled via a hardware strap upon reset The rtl8316 provides a broadcast storm filtering function which is provided to compensate for unusual broadcast storm interference The rtl83 16 port trunking function supports the ability to aggregate four 10/100 ports into a single logical link to increase the bandwidth between the rtl8316 and another device(switch or server with trunking function enabled. Four Trunk groups are supported. The trunk load balance is controlled by the Da/Sa hash algorithm. The load balancing algorithm will make sure that frame distribution does not become mis-ordered, and that there is no frame duplication in the port trunk The rTL83 16 supports 3 types of Qos functions to improve multi-medium or real-time networking applications. They are based on: (1) Port based priority(2)802. lp/Q VLAN priority tag(3)TCP/IP's TOS/DS (DiffServ ) field. The QoS function can be easily enabled or disabled and configured by hardware pins without any eEprom or CPu configuration required There are two output queues on cach output port when Qos is enabled: onc is for high priority frames, the other is for low priority frames. The rTL83 16 supports an intelligent adaptive flow control for high priority frames in order to avoid the flow control function, which can affect the quality of high priority frames such as real-time multi-media application traffic. By setting En FCAutoOff high upon reset, the rtl83 16 will automatically turn off the 802.3x flow control and back pressure flow control for 1-2 sec whenever the port receives high priority frames. Flow control will be re-enabled when no high priorit frames are received during this 1-2 sec duration All system configuration and control hardware pins have a default value, implemented through internal pull-high/low resisters The rtl8316 supports a port based HOME Virtual Local Area Network(VLAN) function for network topology security configuration. When the port bascd sccurity function is enabled, the 16 ports of the rtl83 16 can be configured as 14 individual VLANS that share the same two overlapping ports. Or, the 16 ports can be configured as 15 individual VLANs that share the same one ovcrlapping port. This 14 VLANs or 15 VLANS topology is uscful to allow homc nctworks to sharc a common server or router but be configured as different vlans for security reasons The rtL8316 supports non-blocking 148800 packets/second wire speed forwarding rate and includes a special design to resolve head-of-line-blocking problems. Finally, only one 50MHz OsC is needed for system design 50MH Realtek OSc RTL8316 Oct-PHY or 川 Oct-PHY or 2 Quad-PHY 2 Quad-PHY 10/100 Mbps x16 Example of a 16-port switch system 200I109 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de L5 REALTEK RTL8316 3. Pin Assignments 占 OLu6Q×= 9出豆豆88 点≌苦臣臣臣 隔BE早时式 P6TXD1 P6TXDO/ EnPort Pri[1] P11TXE/ EnValnT ypel 108 VCC P11TXDO P11TXD1 P5RXDC P11 CRSDV 110 P1IRXDO P11RXD1 VCC 113 P12TXE/ EnP14ForceModeL115 P12TXDO P14ForceFCTL P12TXD1 d Gs rtl8316 P12CRSDV P12RXDO 19 P12RXD1 P13TXE/ P14ForceSPD 693765432554346543 59F P5RXD1 P5CRSDV P5TXD1 5TXDO/ En8021pPri P5TXEEnDSPri 53F P4RXD1 P4RXDC P4CRSDV P4TXD1 P4TXDO/ EnF CAub off P4TXE GND VCC P13TXDO/ P14ForceDUPX P3RXD P3RXDC P13CRSDV P3CRSDV P13RXDO 125 42 P3TXD1 P13RXD1 41 P3TXDO EnBKP2BOne P14TXE/ EnP15Force Model 127 P3TXE/ En Trunk 3 P14TXDO/ P15ForceFCTLD1128 P2RXD N寸0只g9g8R8界RR8588期防胃 五正总aa O aO 山 义a 200I109 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de L5 REALTEK RTL8316 4. Pin Description 4.1 RMII Interface(Port #O Port #15) Symbol ype Pin no Description POTXE, RMII Transmit Enable: The rtl8316 asserts high to indicate that PITXE 26, valid data for transmission is presented on the TXD[1: 0]. It is P2TXE synchronous with refCLK P3TXE P4TXE PSTXE P6TXE PTXE 77 P8TXE POTXE 86 PIOTXE PIITXE P12TXE 115 P13TXE 121 P14TXE 127, PISTXE P0TXD[1:0] 19, 18, RMII Transmit Data [1: 0]: The RTL8316 transmit data TXD[1: 0 P1TXD[1:0] 30, 29, is clocked out by the rising edge of REFCLK. P2TXD[1:0] 3635, P3TXD[1: 0 42.41 P4TXD[:0], 50.49, PSTXD[: 0 56.55 P6TXD[1:0] 64,63, P7TXD[1: 0 70,69, P8TXD[1: 01 79.78. P9TXD I: 0 88,87, PIOTXD1: 0 97,96 PIITXD1: 01 109,108 PI2TXD 1: 0 117,116 PI3TXDII: 0 123.122 P14TXDI: 0 P15TXD[1:0 7,6 POCRSDV Co, RMII CRSDV signals: CRSDV from PhY device is asserted high PICRSDV 31. when media is non-idle P2CRSDV 37 P3CRSDV P4CRSDV 51. PSCRSDV P6CRSDV 62 P7CRSDV 71 PSCRSDV P9CRSDV PIOCRSDV PIICRSDV PI2CRSDV 118 PL3CRSDV 124 P14CRSDV 2 P1SCRSDV 8 200I109 5 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de L5 REALTEK RTL8316 PORXDII: 0] 22, 21,RMII Receive Data(1: 0: The RTL8316 samples the receive data PIRXD[I: 0] 33,32,RXD[L: 0]on the rising edge of REFCLK when CRSDV is high P2RXD 1: 0 39,38 P3RXD[I: 01 45,4, P4RXD[L: 0 53,52, P5RXD1: 0 59.58 P6RXD[L: 0 67,6, P7RXD[: 0] 73,72, P&RXDI: 0 82,81, P9RXD[1: 0] 91,90, PIORXDII: O 10099, PIIRXDII: O], 112,11, P12RXD[1: 0 120,119 P13RXD[:0] 126.125 P14RXD[:0], 4,3, PI5RXDI1: 0 10,9 REFCLK 92 RMII Reference Clock input: A 50 MHz signal is used for the RMiI clock reference and is used to generate an internal 66 Mhz system clock 4.2 Serial Management Interface Symbol Type Pin No Description MDC 74 Serial Management Data Clock: Tri-state when RST# is active (P-up) MDIO L/O 75 Serial Management Data Input/Output: Tri-state when RST# (P-up) active low 4.3 System pins Symbol Type Pin n Description RST# 76 System Reset: Active low to reset the system to a known state.After (P-up) power-on reset (low to high), the configuration modes from Mode Pins are sampled and determined, then rtL8316 will start to access the management register of Phy devices and restart the 4. 4 Mode control pins Symbol Type Pin No Description EnP14 Force Mode P12TXE Port 14 Force Mode Setup Enable: Pulled high upon reset will (P-down enable port 14 to set flow control, duplex mode and speed by P14FCTRL, P14DUPLEX and P14SPEED pins separatel Otherwise, these setups will depend on port 14 auto-negotiation Enable force mode setting 0: Disable force mode setting Default) P14ForceFCTRL P12TXDO Port 14 Flow Control Force Mode Setup: During RST# rising (P-up) edge, if EnP14ForceMode-High, this pin acts as port 14s flow ntrol fo 1: Force enable flow control. (Default) 0: Force disable flow control P14ForceDUPLEX P13TXDO Port 14 Duplex Force Mode Setup: During RST# rising edge, if up EnP14Force- High, this pin acts as port 14s duplex force mode up pin se 1: Force full duplex mode (default) 10: Force half duplex mode 200I109 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de L5 REALTEK RTL8316 P14ForceSPEED P13TXE Port 14 Speed Force Mode Setup: During RST# rising edge, if (P-up) EnP14ForceMode =lligh, this pin acts as port 14s speed force mode setup pin sct as below 1: Forcc 100 Mbps speed (default) 0: Forcc 10 Mbps spccd Enpl5Force Mode P14TXE Port 15 Force Mode Setup Enable: Pulled high upon reset will P-down enable port 15 to set flow control, duplex mode and speed b P15FCTRL, PISDUPLEX and PlsSPEED pins separately. Otherwise the setup will depends on port 15s auto-negotiation results I: Enable force mode sctti 0: Disable force mode setting (default) P1SForceFCTRL P14TXDO Port 15 Flow Control Force Mode Setup: During RSI# rising edge, if EnPl5ForceMode =lligh, this pin acts as port 15s flow control force mode setup pin sct as bclow: 1: Force enable flow control(default) 0: Force disable flow control PlSForceDUPLEX I P15TXDO Port 15 Duplex Force Mode Setup: During RST# rising edge, if (P-up) EnP15ForceMode=lligh, this pin acts as port 15s duplex force mode setup pin set as below 1: Force full duplex mode(default) 0:Force half duple PlSForceSPEED P15TXE Port 15 Speed Force Mode Setup: During RST# rising edge, if (P-up) EnP15forceMode=lligh, this pin acts as port 1 5s speed force mode setup pin set as below I: Force 100 Mbps speed( default) 0:Force 10 Mbps speed ENBRDCTRL PgTXE Enable Broadcast Storm Filtering Control: Pulled high upon reset (P-down) will enable the broadcast storm control function. Pulled low upon reset will disable the broadcast storm control function EnctrlFrame Filter P8TXDO Enable 802.1D specified reserved group MAC addresses fral (P-down) filtering: When network control frames are received with the destination MAC address as a group MAC address: (01-80-C2-00-00-03 01-80-C2-00-00-0F), the rtl83 16 will drop the frames if the EnCtrlFrameFilter is set. Otherswise it will be flooded The value of EnCtrlF'ramelilter is trapped on the power on reset 1: Enable drop 0: Disable drop (default EnbKPrs P1OTXE Enable Back pressure flow control function During hardware reset, the pull-high/low value will control the Back pressure flow control function 1: Enable back pressure( default) 0: Disable back pressure ENFDFCTRL P9TXDO Enable Full Duplex 802.3x Flow Control: Pulled high upon reset will enable the full duplex IEEE802.3x flow control function. The tlow control ability will be written to management register 4 of the PHY device once(and only once) after power-on reset, for advertising Pulled low upon reset will disable the full duplex flow control function ENTRUNKO PITXDO Enable Port Trunk 0: Pulled high upon reset will enable port trunk (P-down) 0 which consists of ports 0, 1, 2, 3 ENTRUNKI LO P2TXE Enable Port Trunk 1: Pulled high upon reset will enable port trunk (P-down) I which consists of ports 4, 5,6,7. ENTRUNK2 LO P2TXD0 Enable Port Trunk 2: Pulled high upon reset will enable port trunk (P-down 2 which consists of ports 8, 9, 10, 11 ENTRUNK3 I/0 P3TXE Enable Port Trunk 3: Pulled high upon reset will enable port trunk (P-down) 3 which consists of ports 12, 13. 14,15 200I109 7 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de L5 REALTEK RTL8316 ENVLAN POTXDO Enable Port Based VLAN configuration function: Latched during (P-down) hardware reset. The vlan topology is control by Vlanlype pin, but will be disabled if the trunking function is enabled 1: Enable the VLAN function on cach port 0: Disable the vlan function on cach 16 ports( default) Vlan type P1ITXE VLAN topology type selection to select 14 VLANS or 15 P-down VLANs topology. During hardware reset, the pull-high/low value will control the HOME VLAN topology type 1: Sclect 15 VALNS(port#0-14)with I overlapping port (port #15)topology 0: Sclect 14 VLANS(port#0-13)with 2 overlapping ports (port #14, 15)topology (default) EnPortPri[l: 0I P6TXDO, Enable Port based priority QoS function: Latched during (P-down, P6TXE] hardware resct Sctting as follows: P-down) 00: Disable port based priority(default) Set porthO-I as high priority ports (2 ports) 10: Set port#0-3 as high priority ports.(4 ports Set port#0-7 as high priority ports.(& ports) En802lpPri P5TXDO Enable 802. 1p VLAN Tag priority based QoS function: Latched P-down) ring ardware reset I: Enabled Disabled (default) EndSPri P5TXE Enable TCP/IP TOS/DS(DiffServ) based QoS function: Latched (P-down during hardware reset 1: Enabled High Priority: if TOS,Ds0: 5 (EF)"10110o; (AI)"001010","o10010", "o1lo10","100010 (Network Control) 11x000 Low Priority: if TOS/DS=other 0: Disabled(default) (DS- Differentiated Service) QWEIGHT[I: 0 [P7TXDO, Weighted round robin ration of priority queue: Latched during (P-up, P7TXE] hardware reset P-up The frame service rate High-pri queue: Low-pri queue I I= always high priority queue first(default) 10=8:1 01=4:1 EnF Cautooff P4TXDO Enable Flow Control Ability Auto Turn Off: Latched during (P-down hardware reset. Enable Auto turn off low priority queue's flow control ability 1 2 seconds whenever th e port received a high priority frame. The flow control ability will be re-enabled when no high priority frames are received for the 1-2 second period I: Enabled 0: Disabled 200I109 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de L5 REALTEK RTL8316 4.5 LED Pins Symbol ype Pin no Description TRUNKLEDO# 10 Port Trunk 0 Status LED: After reset, this pin acts as the port trunk (P-down) O status LED. The LED will be active low when port trunk 0 is enabled. It will blink for 250ms on and 250ms oFF when an. physical port link failures occur within the enabled port trunk. It is dark when port trunk 0 is disabled TRUNKLEDI# O 102 Port Trunk 1 Status LED: After reset, this pin acts as the port trunk (P-down I status LED. The LEd will be active low when port trunk 1 is enabled. It will blink for 250ms On and 250ms OFF when any physical port link failures occur within the enabled port trunk. It is dark when port trunk I is disabled TRUNKLEDZ# /O 103 Port Trunk 2 Status LED: After reset, this pin acts as the port trunk (P-down 2 Status LED. The LEd will be active low when port trunk 2 enabled. It will blink for 250ms ON and 250ms OFF when any physical port link failures occur within the enabled port trunk. It is dark when port trunk 2 is disabled TRUNKLED3# 1/O 104 Port Trunk 3 StatuS LED: After reset, this pin acts as the port trunk (P-down 3 status LED. The LEd will be active low when port trunk 3 enabled. It will blink for 250ms On and 250ms OFF when any physical port link failures occur within the enabled port trunk. It is dark when port trunk 3 is disabled 4.6 Power/ ground pins Symbol Type Pin No Description Ⅴ CC for lc&Core 24,46,60,Digital Power Supply(7 pins) 84.93 GND for l/o& Core 25, 47, 61, Digital Ground (7 pins 106,114 VCC for embedded DRAM 12,16,28 Embedded DRAM Power Supply (3 pins) GnD for embedded dram 11.15,27 Embedded DRAM Ground (3 pins) 4.7 Test pins Symbol Iype Pin no Description EnAccepterr P4TXE Enable Accept Error Packets: Enables the rtL8316 to accept error (P-down) packets and forward them to the destination port. But the acceptable error packet is only limited to 641536 bytes Note: Used for testing only Do Not pull-up this pin ENBKP2SONE P3TXDoRealtek Internal Test Pin: Please back up an external 10K pull low (P-up) resister for advanced configuration and testing Dsc Thrtest POTXE Realtek Internal Test Pin: Please back up an external l0K pull up (P-down) resister for advanced configuration and testing. NC( Comp Test) P1OTXDO Realtek Internal Test Pin: Please back up an external 10K pull low (P-up) resister for advanced configuration and testing NC(DRAMPWTest O 13,23Realtek Internal Test Pin: Please keep these pins floating. NC(ExtcKITest) Realtek Internal Test Pin: Please keep this pin floating. NC(ExtCKsTest PITXE Rcaltck Internal Test Pin: Please keep this pin floating (P-down) NO 14Reserved: Pleasc keep this pin floating. 200I109 9 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de L5 REALTEK RTL8316 5. Block Diagram 16 Ports RMIL RMII PHY LED Management IF 10/100 10/100 LF MAC MAC EDORAM Packet Buffer IF RXFIFO TXFIFO (4 Mbits FIFOS QUEUE DMA Flow Engine TX Start Addr Control Queue Page RX/TX FPP EPP Pointer FIFOS FIFO Switching pacc logIc Flow control 8K-ent Address Table Address-Lookup 128-entry AddreSs CaM Engine EPP Buffer 上HFO anager 200I109 10 Rev 1.72 Tel: +49(0)234-9351135. Fax: +49(0)234-9351137 EMAIL: info acornelius-consult de http://www.cornelius-consult.de

...展开详情
试读 22P RTL8316 芯片资料
立即下载 低至0.43元/次 身份认证VIP会员低至7折
    一个资源只可评论一次,评论内容不能少于5个字
    wanghui00001 和百度资料相同,还不错
    2018-02-26
    回复
    关注 私信 TA的资源
    上传资源赚积分,得勋章
    最新推荐
    RTL8316 芯片资料 38积分/C币 立即下载
    1/22
    RTL8316 芯片资料第1页
    RTL8316 芯片资料第2页
    RTL8316 芯片资料第3页
    RTL8316 芯片资料第4页
    RTL8316 芯片资料第5页
    RTL8316 芯片资料第6页
    RTL8316 芯片资料第7页

    试读已结束,剩余15页未读...

    38积分/C币 立即下载 >