loginid=huangchen@vsunmobile.com,time=2016-04-16 12:20:00,ip=113.99.87.197,doctitle=MT6737 LTE Smartphone Application Processor Functional Specification V1.0.pdf,company=VSUN_WCX
MT6737
LTE Smartphone Application Processor
Functional Specification
Confidential A
MediaTek Confidential © 2016 MediaTek Inc.
Page 5 of 288
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Table 2-12. Mode selection ......................................................................................................................... 68
Table 2-13. Constant tied pins ................................................................................................................... 68
Table 2-14. Baseband downlink specifications .......................................................................................... 71
Table 2-15. Baseband downlink specifications .......................................................................................... 73
Table 2-16. LTE_BBTX specifications ........................................................................................................ 75
Table 2-17. C2K_BBTX specifications ........................................................................................................76
Table 2-18. ETDAC specifications .............................................................................................................. 77
Table 2-19. APC-DAC specifications .......................................................................................................... 78
Table 2-20. Definitions of AUXADC channels ...........................................................................................79
Table 2-21. AUXADC specifications .......................................................................................................... 80
Table 2-22. Clock squarer specifications .................................................................................................... 81
Table 2-23. ARMPLL specifications .......................................................................................................... 84
Table 2-24. MAINPLL specifications ........................................................................................................ 84
Table 2-25. MMPLL specifications ............................................................................................................ 84
Table 2-26. UNIVPLL specifications ......................................................................................................... 85
Table 2-27. MSDCPLL specifications ........................................................................................................ 85
Table 2-28. WPLL specifications ............................................................................................................... 85
Table 2-29. WHPLL specifications ............................................................................................................ 86
Table 2-30. C2KCPPLL specifications ....................................................................................................... 86
Table 2-31. C2KDSPPLL specifications ..................................................................................................... 86
Table 2-32. CR4PLL specifications ............................................................................................................ 87
Table 2-33. VENCPLL specifications ........................................................................................................ 87
Table 2-34. TVDPLL specifications ........................................................................................................... 87
Table 2-35. LTEDSPPLL specifications ..................................................................................................... 88
Table 2-36. APLL1 specifications ............................................................................................................... 88
Table 2-37. Temperature sensor specifications ........................................................................................ 89
Table 2-38. Thermal operating specifications .......................................................................................... 90
Table 3-1. Interrupt request list for Cortex-A53 ....................................................................................... 93
Table 3-2. Memory map of on-chip memory controller ......................................................................... 100
Table 3-3. External interrupt request signal connection ....................................................................... 104
Table 3-4. Definitions of domains ........................................................................................................... 104
Table 3-5. EINT table ............................................................................................................................... 104
Table 3-6. DRAM bus signal list (refer to DRAMC side) ......................................................................... 114
Table 3-7. DRAM bus command truth table (LPDDR2/3) ..................................................................... 115
Table 3-8. Relationship between engines and devices ............................................................................ 119
Table 4-1. PLL related control................................................................................................................... 126
Table 4-2. Clock gating settings ................................................................................................................ 126
Table 5-1. SPI controller interface ............................................................................................................ 153
Table 5-2. AUXADC: feature list .............................................................................................................. 160
Table 5-3. AUXADC: design partition ...................................................................................................... 162
Table 5-4. Operation mode of GPT ........................................................................................................... 169
Table 5-5. Interface of audio sys .............................................................................................................. 188
Table 6-1. Base addresses of SMI local arbiters ....................................................................................... 196
Table 6-2. Input format list ....................................................................................................................... 199
Table 6-3. Functional specifications of resizers ...................................................................................... 203
Table 6-4. Hardware specifications of resizers ....................................................................................... 204
Table 6-5. ROT_DMA OFST_ADDR settings for rotation/flip .............................................................. 212
Table 6-6. VIDO UV SEL for YUV420 format cooperated with CRSP ................................................... 213
Table 6-7. Data map ................................................................................................................................. 244
