Vivado下用Verilog编写的带冒险的5级MIPS流水线设计

2015.2: * Version 8.2 (Rev. 6) * Internal device family change, no functional changes 2015.1: * Version 8.2 (Rev. 5) * Delivering non encrypted behavioral models * Supported memory depth is increased up to 1M words * Added the power saving feature (RDADDRCHG) for ultrascale devices * Supported devices and production status are now determined automatically, to simplify support for future devices 2014.4.1: * Version 8.2 (Rev. 4) * Updated the IP to support the device package changes 2014.4: * Version 8.2 (Rev. 3) * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time * Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices * Internal device family change, no functional changes 2014.3: * Version 8.2 (Rev. 2) * Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used * Fixed the GUI crash in Simple Dual Port RAM * Added support of all write modes in Simple Dual Port RAM when ECC is not used * Increased the supported depth to a maximum value of 256k 2014.2: * Version 8.2 (Rev. 1) * Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI 2014.1: * Version 8.2 * Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices * Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices * Added support of the dynamic power saving for ultra-scale devices * Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices * Internal device family name change, no functional changes 2013.4: * Version 8.1 * The Primitive output registers are made "ON" by default in the stand alone mode * Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives * Added support for ultrascale devices 2013.3: * Version 8.0 (Rev. 2) * Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator. * Improved GUI speed and responsivness, no functional changes * Reduced synthesis and simulation warnings * Added support for Cadence IES and Synopsys VCS simulators * Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN" * Changed BRAM Interface DIN and DOUT to match bus interface directions. 2013.2: * Version 8.0 (Rev. 1) * No Changes 2013.1: * Version 8.0 * Native Vivado Release * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. (c) Copyright 2002 - 2015 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.