The two dominant high-speed chip-to-chip interface protocols for networking applications
are XAUI  and SPI4.2 . While SPI4.2 offers important advantages in channelization,
programmable burst sizes, and per-channel backpressure, the excessive width of the
interface limits its scalability, and the source-synchronous nature of th
e protocol reduces its
effective reach. Conversely, XAUI is a narrow 4-lane interface, offers long reach, and suits a
variety of implementations: FR4 on PCB, backplanes, and cable. Yet as a packet-based
interface it lacks channelization and flow control, restricting it from several applications. And
both protocols offer only fixed configurations, limiting the ability of the designer to tailor the
interface capacity to the application.
This document defines a new protocol, Interlaken, that enables the design of a narrow,
high-speed, channelized packet interface.