用verilog实现HDB3编解码的程序

module hdb(clk0,din,clkM,m_out,hdb_out,dpll,out,rz1,rz0,rd);
input clk0;
input [7:0] din;
output[7:0] hdb_out;
output clkM;
output m_out;
output dpll;
output[7:0]out;
output rz1;
output rz0;
output rd;
reg[7:0]hdb_out;
reg[7:0]temp;
reg data_in;
reg[3:0]buffer;
reg parity;
reg judge_v;
reg en_cnt;
reg last_sign;
reg[2:0] cnt;
reg[1:0]data_out;
reg b;
reg[7:0]random;
reg[7:0]all_zero;
reg clk;
reg[7:0]temp0;
assign m_out=data_in;
assign dpll=0;
assign rz0=0;
assign rz1=0;