1998 Microchip Technology Inc.
Preliminary
DS21206B-page 4-3
93C56A/B
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device. A low level deselects
the device and forces it into standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the CS input signal. If CS is
brought low during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
CS must be low for 250 ns minimum (T
CSL
) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
CKH
) and
clock low time (T
CKL
). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
2.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (T
PD
after the positive
edge of CLK).
This pin also provides READY/B
USY status informa-
tion during ERASE and WRITE cycles. READY/B
USY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
CSL
) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on
DO, if CS is held low during the entire ERASE or
WRITE cycle. In this case, DO is in the HIGH-Z mode.
If status is checked after the ERASE/WRITE cycle, the
data line will be high to indicate the device is ready.
.
Note:
CS must go low between consecutive
instructions.
TABLE 2-1: INSTRUCTION SET FOR 93C56A
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)12
ERAL
1 00 10XXXXXXX — (RDY/BSY)12
EWDS
1 00 00XXXXXXX — HIGH-Z 12
EWEN
1 00 11XXXXXXX — HIGH-Z 12
READ
1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20
WRITE
1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)20
WRAL
1 00 01XXXXXXXD7 - D0 (RDY/BSY)20
TABLE 2-2: INSTRUCTION SET FOR 93C56B
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11
ERAL
1 00 10XXXXXX — (RDY/BSY)11
EWDS
1 00 00XXXXXX — HIGH-Z 11
EWEN
1 00 11XXXXXX — HIGH-Z 11
READ
1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27
WRITE
1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27
WRAL
1 00 01XXXXXXD15 - D0 (RDY/BSY)27
