ARM结构(ARM公司提供).pdf

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arm architecture reference manual
Preface This preface describes the versions of the aRM architecture and the contents of this manual, then lists the conventions and terminology it uses About this manual on page iv Architecture versions and variants on page v Using this manual on page x Conventions on page xii ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved Preface About this manual The purpose of this manual is to describe the arM instruction set architecture, including its high code density Thumb subset, and two of its standard coprocessor extensions The standard System Control coprocessor(coprocessor 15), which is used to control memory system components such as caches, write buffers, Memory Management Units, and Protection Units The Vector Floating-Point (VFP)architecture, which uses coprocessors 10 and 1 l to supply a high-performance floating-point instruction set These instruction sets are described primarily from the viewpoint of the instruction being a 32-bit word or 16-bit halfword. The precise effects of each instruction are described, including any restrictions on its use This information is of primary importance to authors of compilers, assemblers, and other programs that generate ARM machine code Assembler syntax is given for most of the instructions described in this manual, allowing instructions to be specified in textual form This is of considerable use to assembly code writers, and also when debugging either assembler or high-level language code at the single instruction leve Howcver, this manual is not intended as tutorial matcrial for ARM assembler language, nor docs it describe ARM assembler language at anything other than a very basic level. To make effective use of ArM assembler language, consult the documentation supplied with the assembler being used. Different assemblers vary considerably with respect to many aspects of assembler language, such as which assembler directives are accepted and how they are coded A considerable amount of generic information is also included about how arm processors access memory and othcr systcm componcnts. Although this usually nccds to bc supplemented by dctailcd implementation-specific information from the technical reference manual of the device being used, this infornation is of use to designers ofARM-based systems Copyright C 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E Preface Architecture versions and variants The aRM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. These are denoted by the version numbers l to 5 Many of the versions can be qualified with variant letters to specify collections of additional instructions that are included in that version. These collections vary from being very small (the M variant denotes the addition of just four extra instructions )to very large(the T variant denotes the addition of the entire Thumb struction set) Thc fivc versions of the arm instruction sct architecture to datc arc as follows: Version 1 This version was implemented only by ARMl, and was never used in a commercial product It contained the basic data-processing instructions(not including multiplies) byte. word, and multi-word load/store instruct branch instructionS, including a branch-and-link instruction designed for subroutine a software interrupt instruction, for use in making Operating System calls Version I only had a 26-bit address space, and is now obsolete Version 2 This version extended architecture version I by adding multiply and multiply-accumulate instructions coprocessor support two more banked registers in fast interrupt mode atomic load-and-storc instructions called SWP and SWPB (in a slightly latcr variant called version 2a) Versions 2 and 2a still only had a 26-bit address space, and are now obsolete Version 3 This architecture version extended the addressing range to 32 bits. Program status information which had previously been stored in r15 was moved to a new Current program Status Register(CPSR), and Saved program Status Registers(SPSRs) were added to preserve the CPSR contents when an exception occurred. As a result, the following changes occurred to the instruction set two instructions(MRS and msr)were added to allow the new cPsr and spsrs to be the functionality of instructions previously used to return from exceptions was modified to allow them to continue to be used for that purpose Version 3 also added two new processor modes in order to make it possible to use Data Abort, Prefetch Abort and Undefined Instruction exceptions effectively in Operatin Systein code Backwards-compatibility support for the 26-bit architectures was obligatory in version 3 except in a variant called version 3G. The distinction belween versions 3 and 3G is no obsolete ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved Prefab Version 4 This version extended architecture version 3 by adding halfword load/store instructions instructions to load and sign- extend bytes and halfwords in t variants. an instruction to transfer to thumb state a new privileged processor mode that uses the User mode registers Version 4 also made it clearer which instructions should cause the Undefined Instruction exception to be taken Backwards-compatibility support for 26-bit architectures ceased to be obligatory in version 4 Version 5 This version extends architecture version 4 by adding instructions and slightly modifying the definitions of some existing instructions to improve the efficiency of ARM/Thumb interworking in T variants allow the same code generation techniques to be used for non-T variants as for t variants Version 5 also adds a count leading zeros instruction, which (among other things )allows more efficient integer divide and interrupt prioritization routines adds a softwarc breakpoint instruction adds more instruction options for coprocessor designers tightens the definition of how flags are set by multiply instructions The Thumb instruction set (T variants) The Thumb instruction set is a re-encoded subset of the arm instruction set. Thumb instructions are hall the size of ARM instructions(16 bits compared with 32), with the result that greater code density can usually be achieved by using the thumb instruction set instead of the arm instruction set. The Thumb instruction set is described in detail in Chapter ab The Thumb Instruction Set and Chapter a/ Thumb instructions Two limitations of the Thumb instruction sct comparcd with the aRM instruction sct arc Thumb code usually uses more instructions for the same job so ARM code is usually best for maximizing the performance of time-critical code The Thumb instruction set does not include some instructions that are needed for exception handling, So ARM code needs to be used for at least the top-level exception handlers Because of the second of these, the Thumb instruction set is always used in conjunction with a suitable version of the Ar instruction set. Its presence is denoted by the variant letter T, and it is not valid prior to ARM architecture version 4 Copyright C 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E Preface Thumb instruction set versions There arc two versions of the Thumb instruction sct Thumb version l is used in t variants of arm architecture version 4 Thumb version 2 is used in t variants of arm architecture version 5 Compared with Thumb version 1, Thumb version 2 adds instructions and slightly modifies the definition of some existing instructions to improve the efficiency of ARM/Thumb interworking adds a sofiware breakpoint instruction tightens the definition of how the Thumb multiply instruction sets the flags These improvements are closely related to the changes between ARM architecture versions 4 and 5 In gencral, the Thumb instruction sct version number is not uscd in this manual. Instcad the vcrsion numbcr of the associated version of the aRM instruction set is used, to allow easy use with the naming scheme described in Naming ofARM/Thumb architecture versions on page viii Long multiply instructions(M variants) M variants of the ARM instruction set include four extra instructions which perform 32 X 32->64 multiplications and 32 x 32+64>64 multiply-accumulates. These instructions imply the existence of a multiplier that is significantly larger than minimum, and so are sometimes omitted in implementations for Thich a small dic sizc is vcry important and multiply pcrformance is not vcry important. Thcir prcscncc is denoted by the use of the variant letter m These instructions were first defined as a variant of architecture version 3 and are included in similar variants of later architecture versions. Because the combination of requirements that leads to them being excluded does not arise very often in practice, inclusion of these instructions is standard in architecture versions 4 and above Enhanced DSP instructions(E variants) E variants ofthe ARM instruction set include a number of extra instructions which enhance the performance ofan arM processor on typical digilal signal processing(dsp)algorithIns. These instructions are described in detail in Chapter A10 Enhanced DSP Extension, and include: Several new multiply and multiply-accumulate instructions that act on 16-bit data items Addition and subtraction instructions that perform saturated signed arithmetic. This is a form of integer arithmetic that produces the maximum negative or positive value instead of wrapping around if the calculation overflows the normal integer range ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved Preface Load (DRD), store(STRD)and coprocessor register transfer(MCrR and mrrc instructions that act 2 words of dat A cache preload instruction PLD These instructions were first defined as a variant of architecture version 5T. Their presence is denoted by the variant letter E, and they are not valid prior to architecture version 5. They are also not valid in non-T or non -M variants of the architecture The arMv5texP architecture version Some early implementations of the enhanced DSP variant of the ARM architecture omitted the LDRD STR, MCRR, MRRC and FlD instructions. Apart from this omission, all the arm implementations concerned implemented the ARMvsTE architecture In order to be able to name this architecture variant the letter p can be used to exclude these five instructions from architecture version ARMYSTE, according to the rules in Naming of ARM/Thumb architecture versions on page viii. The resulting architecture variant is therefore named ARMv5TExP. This is the only use of the p variant letter Naming of ARM/Thumb architecture versions o name a precise version and variant of the aRM Thumb architecture the following strings are concatenated The string ARN 2. The version number of the arm instruction set 3. Variant letters of the included variants, except that the m variant is standard in architecture versions 4 and above, and therefore not normally listed 4. If any variants described as standard in 3 above are not present, the letter x followed by the letters of the excluded variants In addition the letter p can be used after x to denote the exclusion of certain instructions from architecture version ARMy5TE. as described in The ARMy TExp architecture versor The table Architecture versions on page ix lists the standard names of the current(not obsolete ARM/Thumb architecture versions described in this manual. These names provide a shorthand way of describing the precise instruction set implemented by an ARM processor. However, this manual normally uscs descriptive phrases such as "M variants of architecture version 3 and above to avoid the usc of lists of architecture names which are already long and will grow further in the future Obsolete architecture names are ARMvl. ARMy2. ARMv2a and armv3G. These are the versions 1. 2 2a, and 3G described in Architecture versions and variants on page v. Copyright C 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E Prefa Architecture versions ARM instruction Thumb instruction Long multiply Enhanced DSP set version set version instructions? instructions ARMV3 No ARMV3M 3 None Yes N ARMv4XM 4 None N ARMv4 4 None ARMv4TxM 4 N ARMv4T Yes No ARMVSXM None No No ARMVS Yes ARMV5TXM 5 No ARMV5T N ARMV5TEXP 5 2 Yes all but ldrd MCRR MRRC PlD and STRD ARMV5TE 5 2 Yes Yes ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved Preface Using this manual The information in this manual is organized into three parts, as described below Part A-CPU Architectures Part a describes the arm and Thumb instruction sets, and contains the following chapters Chapter al Gives a quick overview of the ARm instruction set Chapter A2 Describes the types of value that ARM instructions operate on, the general-purpose registers that contain those values, and the program Status Registers. This chapter also describes how ARM processors handle interrupts and other exceptions, and contains general information about the memory interface of an ARM processor Chapter A3 Gives a description of the ARM instruction set, organized by type of instruction Chapter A4 Contains detailed reference material on each ARM instruction, arranged alphabetically by Instruction mnemonic Chapter A5 Contains detailed reference material on the addressing modes used by arM instructions The term addressing mode is interpreted broadly in this manual, to mean a procedure shared by many different instructions, for generating values used by the instructions. For four of the addressing modes described in this chapter, the values generated are memory addresses (which is the traditional role of an addressing mode). The remaining addressing mode generates values to be used as operands by data-processing instructions Chapter a6 Gives a description of the Thumb instruction set, organized by type of instruction. This chapter also contains information about how to switch between the ARM and Thumb instruction sets, and how exceptions that arise during Thumb state execution are handled Chapter A7 Contains detailed reference material on each Thumb instruction, arranged alphabetically by instruction mnemonic Chapter as Gives information on the 26-bit architectures (ARMvl, ARMv2, and ARMv2a), and about the backwards-compatibility support for these architectures that is built into some later ARM processors. All of these features are now obsolete, and information about them is only relevant to historical systems Chapter a9 Contains some examples of using the ARM instruction set Chapter alo Gives a description of the extra instructions added in the enhanced dsp extension(see Enhanced DSP instructions(E variants) on page vii) Copyright C 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E

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