用verilog HDL设计交通灯

module JTD(clk, en, lampa, lampb, numa, numb);  
input clk, en;//时钟和复位输入 
output[7:0] numa,numb;//BCD码计数值输出 
output[3:0] lampa, lampb;// 不同颜色交通灯的亮灭控制信号输出
reg[2:0] statea, stateb;//电路当前状态 
reg[7:0] numa, numb; 
reg[3:0] lampa, lampb;
reg[25:0]count; wire clk1hz; 
reg tempa, tempb;// 计数器的计数结束标志 
parameter ared =8'h55,ayellow=8'h5,agreen=8'h40,aleft=8'h15,bred=8'h65,byellow=8'h5, 
bgreen=8'h30,bleft =8'h15;    // 不同颜色灯的点亮秒数 
  
always @(posedge clk)
    begin   if(count==50000000) count<=0;
            else  count<=count+1;
    end
assign clk1hz=count[25];


always @ (posedge clk1hz)  
   begin 
     if (!en)  
      begin  numa<=ared;    lampa<= 4'b1000;    statea<=0;    tempa<=0;   end  
else  
     begin    if (!tempa)             // 计数已结束 
                 begin    
                       case(statea)  
                         0 : begin numa<=agreen;    lampa<=2;    statea<=1;    end  
                         1 : begin numa<=ayellow;    lampa<=4;    statea<=2;    end  
                         2 : begin numa<=aleft;    lampa<=1;    statea<=3;    end