################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
没有合适的资源?快使用搜索试试~ 我知道了~
资源推荐
资源详情
资源评论
收起资源包目录
fpga的fft核测试 (431个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
xfft_0.dcp 1.56MB
xfft_0.dcp 1.56MB
xfft_0.dcp 1.55MB
xfft_0.dcp 1.55MB
fifo_16x1024_bram.dcp 127KB
fifo_16x1024_bram.dcp 127KB
fifo_16x1024_bram.dcp 127KB
fifo_16x1024_bram.dcp 122KB
fifo_16x1024_bram.dcp 111KB
fifo_16x1024_bram.dcp 111KB
fifo_16x1024_bram.dcp 106KB
dds_compiler_0.dcp 102KB
dds_compiler_0.dcp 96KB
dds_compiler_0.dcp 96KB
dds_compiler_0.dcp 95KB
blk_mem_gen_0.dcp 34KB
compile.do 4KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 2KB
compile.do 1KB
compile.do 1KB
compile.do 991B
compile.do 977B
simulate.do 633B
simulate.do 625B
simulate.do 625B
simulate.do 537B
simulate.do 537B
simulate.do 537B
elaborate.do 505B
elaborate.do 409B
simulate.do 356B
simulate.do 356B
simulate.do 353B
elaborate.do 225B
simulate.do 211B
simulate.do 205B
simulate.do 189B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
run.f 2KB
run.f 2KB
run.f 1KB
run.f 1KB
run.f 837B
run.f 809B
xsim.ini 25KB
xsim.ini 25KB
xsim.ini 25KB
vivado.jou 759B
vivado.jou 738B
vivado.jou 683B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 88KB
runme.log 56KB
runme.log 31KB
summary.log 984B
fft.lpr 290B
elab.opt 510B
elab.opt 414B
elab.opt 230B
vivado.pb 117KB
vivado.pb 89KB
vivado.pb 50KB
xfft_0_utilization_synth.pb 289B
dds_compiler_0_utilization_synth.pb 289B
fifo_16x1024_bram_utilization_synth.pb 289B
vlog.prj 153B
vhdl.prj 111B
vhdl.prj 95B
vlog.prj 45B
共 431 条
- 1
- 2
- 3
- 4
- 5
资源评论
- 灵敏度高2021-03-23您好,我下载了工程,但是test文件中的DDS核设置不清楚,请问您一下设置
FPGA入门
- 粉丝: 230
- 资源: 11
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功