Specification for the:
WISHBONE System-on-Chip (SoC)
Interconnection Architecture
for Portable IP Cores
Revision: B.3, Released: September 7, 2002
WISHBONE SoC Architecture Specification, Revision B.3 2
This Page is Intentionally Blank
WISHBONE SoC Architecture Specification, Revision B.3 3
Stewardship
Stewardship for this specification is maintained by OpenCores Organization (hereafter Open-
Cores). Questions, comments and suggestions about this document are welcome and should be
directed to:
Richard Herveille, OpenCores Organization
E-MAIL: rherveille@opencores.org URL: www.opencores.org
OpenCores maintains this document to provide an open, freely useable interconnect architecture
for its own and others’ IP-cores. These specifications are intended to guarantee compatibility be-
tween compliant IP-cores and to improve cooperation among different users and suppliers.
Copyright & Trademark Release / Royalty Release / Patent Notice
Notice is hereby given that this document is not copyrighted, and has been placed into the public
domain. It may be freely copied and distributed by any means.
The name ‘WISHBONE’ and the ‘WISHBONE COMPATIBLE’ rubber stamp logo are hereby
placed into the public domain (within the scope of System-on-Chip design, System-on-Chip fab-
rication and related areas of commercial use). The WISHBONE logo may be freely used under
the compatibility conditions stated elsewhere in this document.
This specification may be used for the design and production of System-on-Chip (SoC) compo-
nents without royalties or other financial obligations to OpenCores.
The author(s) of this specification are not aware that the information contained herein, nor of
products designed to the specification, cause infringement on the patent, copyright, trademark or
trade secret rights of others. However, there is a possibility that such infringement may exist
without their knowledge. The user of this document assumes all responsibility for determining if
products designed to this specification infringe on the intellectual property rights of others.
Disclaimers
In no event shall OpenCores or any of the contributors be liable for any direct, indirect, inciden-
tal, consequential, exemplary, or special damages (including, but not limited to procurement of
substitute goods or services; loss of use, data, or profits; or business interruption) resulting in any
way from the use of this specification. By adopting this specification, the user assumes all re-
sponsibility for its use.
This is a preliminary document, and is subject to change.
Verilog is a registered trademark of Cadence Design Systems, Inc.
WISHBONE SoC Architecture Specification, Revision B.3 4
Document Format, Binding and Covers
This document is formatted for printing on double sided, 8½” x 11” white paper stock. It is de-
signed to be bound within a standard cover. The preferred binding method is a black coil bind-
ing with outside diameter of 9/16” (14.5 mm). The preferred cover stock is Paper Direct part
number KVR09D (forest green) and is available on-line at: www.paperdirect.com. Binding can
be performed at most full-service copy centers such as Kinkos (www.kinkos.com).
Acknowledgements
Like any great technical project, the WISHBONE specification could not have been completed
without the help of many people. The Steward wishes to thank the following for their ideas,
suggestions and contributions:
Ray Alderman
Yair Amitay
Danny Cohan
Marc Delvaux
Miha Dolenc
Volker Hetzer
Magnus Homann
Brian Hurt
Linus Kirk
Damjan Lampret
Wade D. Peterson*
Barry Rice
John Rynearson
Avi Shamli
Rudolf Usselmann
(*) Wade D. Peterson from Silicore Corporation is the original author and steward. Without his dedication this
specification would have never been where it is now.
Revision History
The various revisions of the WISHBONE specification, along with their changes and revision
history, can be found at www.silicore.net/wishbone.htm
.
WISHBONE SoC Architecture Specification, Revision B.3 5
Table of Contents
CHAPTER 1 - INTRODUCTION ............................................................................................................................. 7
1.1 WISHBONE FEATURES ...................................................................................................................................... 8
1.2 WISHBONE OBJECTIVES.................................................................................................................................. 10
1.3 SPECIFICATION TERMINOLOGY .......................................................................................................................... 12
1.4 USE OF TIMING DIAGRAMS ................................................................................................................................14
1.5 SIGNAL NAMING CONVENTIONS ........................................................................................................................ 16
1.6 WISHBONE LOGO............................................................................................................................................ 17
1.7 GLOSSARY OF TERMS......................................................................................................................................... 17
1.8 REFERENCES ...................................................................................................................................................... 29
CHAPTER 2 – INTERFACE SPECIFICATION .................................................................................................. 30
2.1 REQUIRED DOCUMENTATION FOR IP CORES ...................................................................................................... 30
2.1.1 General Requirements for the WISHBONE DATASHEET......................................................................... 30
2.1.2 Signal Naming............................................................................................................................................ 31
2.1.3 Logic Levels ............................................................................................................................................... 32
2.2 WISHBONE SIGNAL DESCRIPTION................................................................................................................... 32
2.2.1 SYSCON Module Signals ........................................................................................................................... 32
2.2.2 Signals Common to MASTER and SLAVE Interfaces ................................................................................ 33
2.2.3 MASTER Signals........................................................................................................................................ 34
2.2.4 SLAVE Signals ........................................................................................................................................... 36
CHAPTER 3 – WISHBONE CLASSIC BUS CYCLES ........................................................................................ 38
3.1 GENERAL OPERATION ........................................................................................................................................ 38
3.1.1 Reset Operation.......................................................................................................................................... 38
3.1.2 Transfer Cycle initiation ............................................................................................................................ 40
3.1.3 Handshaking Protocol ............................................................................................................................... 41
3.1.3 Use of [STB_O].......................................................................................................................................... 44
3.1.4 Use of [ACK_O], [ERR_O] and [RTY_O]................................................................................................. 45
3.1.5 Use of TAG TYPES .................................................................................................................................... 45
3.2 SINGLE READ / WRITE CYCLES .................................................................................................................... 47
3.2.1 SINGLE READ Cycle................................................................................................................................. 47
3.2.2 SINGLE WRITE Cycle ............................................................................................................................... 49
3.3 BLOCK READ / WRITE CYCLES..................................................................................................................... 51
3.3.1 BLOCK READ Cycle.................................................................................................................................. 52
3.3.2 BLOCK WRITE Cycle ................................................................................................................................ 55
3.4 RMW CYCLE .................................................................................................................................................... 58
3.5 DATA ORGANIZATION........................................................................................................................................ 61
3.5.1 Nomenclature............................................................................................................................................. 61
3.5.2 Transfer Sequencing .................................................................................................................................. 64
3.5.3 Data Organization for 64-bit Ports............................................................................................................ 64
3.5.4 Data Organization for 32-bit Ports............................................................................................................ 66
3.5.5 Data Organization for 16-bit Ports............................................................................................................ 67
3.5.6 Data Organization for 8-bit Ports.............................................................................................................. 68
3.6 REFERENCES ...................................................................................................................................................... 68
CHAPTER 4 – WISHBONE REGISTERED FEEDBACK BUS CYCLES ........................................................ 69
4.1 INTRODUCTION, SYNCHRONOUS VS. ASYNCHRONOUS CYCLE TERMINATION ..................................................... 69
4.1 WISHBONE REGISTERED FEEDBACK............................................................................................................... 72
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