eetop.cn_128点 基8 FFT

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FFT/IFFT 128 points IP core

Pipelined FFT/IFFT 128 points (Fast Fourier Transform)

IP Core User Manual

Overview

The FFT128 User Manual contains description of the FFT128 core architecture to explain its

proper use. FFT128 soft core is the unit to perform the Fast Fourier Transform (FFT). It

performs one dimensional 128 – complex point FFT. The data and coefficient widths are

adjustable in the range 8 to 16.

input to output is equal to 310 clock cycles (440 clock cycles when the direct output data

order), simultaneous loading/downloading supported.

 Input data, output data, and coefficient widths are parametrizable in range 8 to 16 and

more.

 Two and three data buffers are selected.

 FFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX35-12 FPGA at

215 MHz clock cycle, and on Xilinx XC5VLX30-3 FPGA at 260 MHz clock cycle,

respectively.

 FFT unit for 10 bit data and coefficients, and 3 data buffers occupies 4147 CLB slices, 4

DSP48 blocks, and 5 kbit of RAM in Xilinx XC4SX35 FPGA, and 1254 CLB slices 4

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FFT/IFFT 128 points IP core

Design Features

Discrete Fourier Transform (DFT) is a fundamental digital signal processing algorithm used

in many applications, including frequency analysis and frequency domain processing. DFT is

the decomposition of a sampled signal in terms of sinusoidal (complex exponential)

components. The symmetry and periodicity properties of the DFT are exploited to

significantly lower its computational requirements. The resulting algorithms are known as

Fast Fourier Transforms (FFTs). An 128-point DFT computes a sequence x(n) of 128

complex-valued numbers given another sequence of data X(k) of length 128 according to the

formula

W128n where: W128 = cos(2/128) – j sin(2/128). The FFT algorithms take advantage of

the symmetry and periodicity properties of W128n to greatly reduce the number of

calculations that the DFT requires. In an FFT implementation the real and imaginary

components of WnN are called twiddle factors.

The basis of the FFT is that a DFT can be divided into smaller DFTs. In the processor

FFT128 a mixed radix 8 and 16 FFT algorithm is used. It divides DFT into two smaller DFTs

of the length 8 and 16, as it is shown in the formula:

X(k) = X(16r+s) =

x(16l+m) W

, r = 0 to 15, s = 0 to 7,

algorithm is illustrated by the graph which is shown in the Fig.1. The input complex data x(n)

are represented by the 2-dimensional array of data x(16l+m). The columns of this array are

computed by 8-point DFTs. The results of them are multiplied by the twiddle factors

W128ms . And the resulting array of data X(16r+s) is derived by 16-point DFTs of rows of

the intermediate result array.

The 8- and 16-point DFTs are implemented by the Winograd small point FFT algorithms,

which provide the minimum additions and multiplications. As a result, the radix-16 FFT

algorithm needs only 128 complex multiplications to the twiddle factors W128ms and a set of

multiplications to the twiddle factors W16sl except of 32768 complex multiplications in the

FFT16 calculates the 8- and 16-point DFTs in the high pipelined mode. Therefore in each

clock cycle one complex number is read from the input data buffer RAM and the complex

result is written in the output buffer RAM. The 8- and 16-point DFT algorithm is divided into

several stages which are implemented in the stages of the FFT8 and FFT16 pipelines. This

supports the increasing the clock frequency up to 200 MHz and higher. The latent delay of

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FFT/IFFT 128 points IP core

the FFT8 unit from input of the first data to output of the first result is equal to 30 clock

cycles. The latent delay of the FFT16 unit from input of the first data to output of the first

result is equal to 30 clock cycles.

In the core the inner data bit width is higher to 4 digits than the input data bit width. The main

64

Besides, the normalizing shifters are attached to the outputs of FFT8 pipelines, which provide

the proper bandwidth of the resulting data. The overflow detector outputs provide the

opportunity to input the proper shift left bit number for these shifters.

The FFT128 processor has the minimum multiplier number which is equal to 4. This fact

makes this core attractive to implement in ASIC. When configuring in Xilinx FPGA, these

multipliers are implemented in 4 DSP48 units respectively. The customer can select the input

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FFT/IFFT 128 points IP core

Signal Description:

The descriptions of the core signals are represented in the table 1.

RST input Global reset

DI [nb-1:0] input Input data imaginary sample

RDY output Result ready strobe

FFTRDY output Input data accepting ready strobe

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FFT/IFFT 128 points IP core

Here DATA_SRC is the data source, for example, the analog-to-digital converter, FFT128 is

the core, which is customized as one with 3 inner data buffers. The FFT algorithm starts with

the impulse START. The respective results are outputted after the READY impulse and

followed by the address code ADDR. The signal START is needed for the global

0,8,16,...56,1,9,17,... .

START

DR

DI

1-st

0-th

0-th