at91sam9260ek裸机调试程序

/* * Driver for NAND support, Rick Bronson * borrowed heavily from: * (c) 1999 Machine Vision Holdings, Inc. * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org> */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include "main.h" #include "com.h" #include "NandFlash.h" #include "nand.h" #include "nand_ids.h" #include "jffs2.h" //************************************************** // Macro definition for NandFlash //************************************************** #define min(x,y) (x < y)?(x):(y) #define max(x,y) (x > y)?(x):(y) #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) /* * Definition of the out of band configuration structure */ struct nand_oob_config { int ecc_pos[6]; /* position of ECC bytes inside oob */ int badblock_pos; /* position of bad block flag inside oob -1 = inactive */ int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */ } oob_config = { {0}, 0, 0}; //#undef NAND_DEBUG #define NAND_DEBUG 1 #undef PSYCHO_DEBUG /* ****************** WARNING ********************* * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will * erase (or at least attempt to erase) blocks that are marked * bad. This can be very handy if you are _sure_ that the block * is OK, say because you marked a good block bad to test bad * block handling and you are done testing, or if you have * accidentally marked blocks bad. * * Erasing factory marked bad blocks is a _bad_ idea. If the * erase succeeds there is no reliable way to find them again, * and attempting to program or erase bad blocks can affect * the data in _other_ (good) blocks. */ #define ALLOW_ERASE_BAD_DEBUG 0 #undef CONFIG_MTD_NAND_ECC /* enable ECC */ #undef CONFIG_MTD_NAND_ECC_JFFS2 /* * Function Prototypes */ void nand_print(struct nand_chip *nand); int nand_rw (struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, size_t * retlen, u_char *buf, u_char *ecc_code); static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, size_t * retlen, const u_char * buf, u_char * ecc_code); void nand_print_bad(struct nand_chip *nand); static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, size_t * retlen, u_char * buf); static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, size_t * retlen, const u_char * buf); static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); #ifdef CONFIG_MTD_NAND_ECC static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); #endif struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; /* Current NAND Device */ int curr_device = -1; /* ------------------------------------------------------------------------- */ static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) { /* This is inline, to optimise the common case, where it's ready instantly */ int ret = 0; #ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ if(ale_wait) NAND_WAIT_READY(nand); /* do the worst case 25us wait */ else udelay(10); #else /* has functional r/b signal */ NAND_WAIT_READY(nand); #endif return ret; } /* NanD_Command: Send a flash command to the flash chip */ static __inline int NanD_Command(struct nand_chip *nand, unsigned char command) { unsigned long nandptr = nand->IO_ADDR; unsigned short wCommand = 0; /* Assert the CLE (Command Latch Enable) line to the flash chip */ NAND_CTL_SETCLE(nandptr); /* Send the command */ if (nand->bus_width_16bit) { wCommand = (unsigned short)command; WRITE_NAND_COMMAND16(command, nandptr); } else WRITE_NAND_COMMAND(command, nandptr); /* Lower the CLE line */ NAND_CTL_CLRCLE(nandptr); #ifdef NAND_NO_RB if(command == NAND_CMD_RESET){ u_char ret_val; NanD_Command(nand, NAND_CMD_STATUS); do{ ret_val = READ_NAND(nandptr);/* wait till ready */ } while((ret_val & 0x40) != 0x40); } #endif return NanD_WaitReady(nand, 0); } /* NanD_Address: Set the current address for the flash chip */ static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) { unsigned long nandptr; int i; unsigned short wMask = 0, wOffset = 0; nandptr = nand->IO_ADDR; /* Assert the ALE (Address Latch Enable) line to the flash chip */ NAND_CTL_SETALE(nandptr); /* Send the address */ /* Devices with 256-byte page are addressed as: * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) * there is no device on the market with page256 * and more than 24 bits. * Devices with 512-byte page are addressed as: * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) * 25-31 is sent only if the chip support it. * bit 8 changes the read command to be sent * (NAND_CMD_READ0 or NAND_CMD_READ1). */ if (nand->bus_width_16bit){ for (i=0; i<nand->page_shift; i++) wMask |= 1 << i; wOffset = ofs & wMask; } if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) for (i = 0; i < nand->columnadrlen; i++){ if (nand->bus_width_16bit) { WRITE_NAND_ADDRESS16(wOffset & 0x00FF, nandptr); } else WRITE_NAND_ADDRESS(ofs, nandptr); if ((nand->columnadrlen != 1) && (i < nand->columnadrlen - 1)) wOffset = wOffset >> 8; } ofs = ofs >> nand->page_shift; if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8){ if (nand->bus_width_16bit) { wOffset = ofs; WRITE_NAND_ADDRESS16(wOffset & 0x00FF, nandptr); } else WRITE_NAND_ADDRESS(ofs, nandptr); } /* Lower the ALE line */ NAND_CTL_CLRALE(nandptr); /* Wait for the chip to respond */ return NanD_WaitReady(nand, 1); } /* NanD_SelectChip: Select a given flash chip within the current floor */ static __inline int NanD_SelectChip(struct nand_chip *nand, int chip) { /* Wait for it to be ready */ return NanD_WaitReady(nand, 0); } /* ------------------------------------------------------------------------- */ /* returns 0 if block containing pos is OK: * valid erase block and * not marked bad, or no bad mark position is specified * returns 1 if marked bad or otherwise invalid */ int check_block(struct nand_chip* nand, unsigned long pos) { int retlen; uint8_t oob_data; int page0 = pos & (-nand->erasesize); int page1 = page0 + nand->oobblock; int badpos = oob_config.badblock_pos; if (pos >= nand->totlen) return 1; if (badpos < 0) return 0; /* no way to check, assume OK */ /* Note - bad block marker can be on first or second page */ if (nand_read_oob(nand, page0 + badpos, 1, (size_t *)&retlen, &oob_data) || oob_data != 0xff || nand_read_oob(nand, page1 + badpos, 1, (size_t *)&retlen, &oob_data) || oob_data != 0xff) { #ifdef NAND_DEBUG printf(" 0x%8.8lx\n\r", badpos); #endif return 1; } return 0; } /* print bad blocks in NAND flash */ void nand_print_bad(struct nand_chip* nand) { unsigned long pos; for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { if (check_block(nand, pos)) { #ifdef NAND_DEBUG printf(" 0x%8.8lx\n", pos); #endif } } #ifdef NAND_DEBUG puts("\n"); #endif } /* cmd: 0: NANDRW_WRITE write, fail on bad block * 1: NANDRW_READ read, fail on bad block * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks */ int nand_rw (struct nand_chip* nand, int cmd,