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<html xmlns="http://www.w3.org/1999/xhtml"><head><meta charset="utf-8"><meta name="generator" content="pdf2htmlEX"><meta http-equiv="X-UA-Compatible" content="IE=edge,chrome=1"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/base.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css"><link rel="stylesheet" href="https://csdnimg.cn/release/download_crawler_static/12968428/raw.css"><script src="https://csdnimg.cn/release/download_crawler_static/js/compatibility.min.js"></script><script src="https://csdnimg.cn/release/download_crawler_static/js/pdf2htmlEX.min.js"></script><script>try{pdf2htmlEX.defaultViewer = new pdf2htmlEX.Viewer({});}catch(e){}</script><title></title></head><body><div id="sidebar" style="display: none"><div id="outline"></div></div><div id="pf1" class="pf w0 h0" data-page-no="1"><div class="pc pc1 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/12968428/bg1.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y3 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y4 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y6 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y7 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y8 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y9 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x3 h3 ya ff2 fs1 fc0 sc0 ls0 ws0">A40i User Manual </div><div class="t m0 x4 h4 yb ff2 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h4 yc ff2 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h4 yd ff2 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h4 ye ff2 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h4 yf ff2 fs2 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 h4 y10 ff2 fs2 fc0 sc0 ls0 ws0">Revision 1.1 </div><div class="t m0 x6 h5 y11 ff2 fs2 fc0 sc0 ls0 ws0">Jun. 15, 2018 </div><div class="t m0 x2 h6 y12 ff1 fs3 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h6 y13 ff1 fs3 fc0 sc0 ls0 ws0"> </div><div class="t m0 x7 h2 y14 ff1 fs0 fc0 sc0 ls0 ws0">Copyright © 2018 Allwinner Technology Co., Ltd. All Rights Reserved. </div></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div></body></html>

<div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/12968428/bg2.jpg"><div class="t m0 x8 h7 y15 ff3 fs4 fc0 sc0 ls0 ws0"> Revision History </div><div class="t m0 x2 h8 y16 ff1 fs4 fc0 sc0 ls0 ws0">A40i User Manual(Revision 1.1) Copyright© 2018 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 3 </div><div class="t m0 x2 h8 y17 ff1 fs4 fc0 sc0 ls0 ws0"> </div><div class="t m0 x9 h9 y18 ff2 fs5 fc0 sc0 ls0 ws0">Revision History </div><div class="t m0 x2 h2 y19 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 ha y1a ff2 fs0 fc0 sc0 ls0 ws0">Revision Date Description </div><div class="t m0 x2 ha y1b ff1 fs0 fc0 sc0 ls0 ws0">1.0 May.22,2018 Initial release version </div><div class="t m0 x2 h2 y1c ff1 fs0 fc0 sc0 ls0 ws0">1.1 Jun.15,2018 </div><div class="t m0 xa ha y1d ff2 fs0 fc0 sc0 ls0 ws0">Chapter 3 System </div><div class="t m0 xa hb y1e ff1 fs0 fc0 sc0 ls5 ws0">1. Add notes about clock tree in Section 3.3.2.1. </div><div class="t m0 xa hb y1f ff1 fs0 fc0 sc0 ls5 ws0">2. Add guide about spread spectrum function in Section 3.3.2.7. </div><div class="t m0 xa hb y20 ff1 fs0 fc0 sc0 ls5 ws0">3. Add operations and functional descriptions, programming guidelines for </div><div class="t m0 xb h2 y21 ff1 fs0 fc0 sc0 ls0 ws0">Timer module in Section 3.7. </div><div class="t m0 xa hb y22 ff1 fs0 fc0 sc0 ls5 ws0">4. Add operations and functional descriptions, programming guidelines for </div><div class="t m0 xb h2 y23 ff1 fs0 fc0 sc0 ls0 ws0">High Speed Timer module in Section 3.8. </div><div class="t m0 xa hb y24 ff1 fs0 fc0 sc0 ls5 ws0">5. Add operations and functional descriptions, programming guidelines for </div><div class="t m0 xb h2 y25 ff1 fs0 fc0 sc0 ls0 ws0">RTC module in Section 3.11. </div><div class="t m0 xa hb y26 ff1 fs0 fc0 sc0 ls5 ws0">6. Add programming guidelines for KEYADC module in Section 3.13. </div><div class="t m0 xa hb y27 ff1 fs0 fc0 sc0 ls5 ws0">7. Add programming guidelines for Thermal Sensor module in Section 3.15. </div><div class="t m0 xa hb y28 ff1 fs0 fc0 sc0 ls5 ws0">8. Add block diagram, operations and functional descriptions for RTC </div><div class="t m0 xb h2 y29 ff1 fs0 fc0 sc0 ls0 ws0">module in Section 3.18. </div><div class="t m0 xa ha y2a ff2 fs0 fc0 sc0 ls0 ws0">Chapter 4 Memory </div><div class="t m0 xa hb y2b ff1 fs0 fc0 sc0 ls5 ws0">1. Add programming guidelines about NDFC in Section 4.2.4. </div><div class="t m0 xa hb y2c ff1 fs0 fc0 sc0 ls5 ws0">2. Add programming guidelines about SMHC in Section 4.3.4. </div><div class="t m0 xa ha y2d ff2 fs0 fc0 sc0 ls0 ws0">Chapter 7 Display </div><div class="t m0 xa hb y2e ff1 fs0 fc0 sc0 ls5 ws0">1. Add BT656 using guides in Section 7.2.4. </div><div class="t m0 xa ha y2f ff2 fs0 fc0 sc0 ls0 ws0">Chapter 8 Interfaces </div><div class="t m0 xa hb y30 ff1 fs0 fc0 sc0 ls5 ws0">1. Add SPI data transfer/receive process in CPU and DMA mode in Section </div><div class="t m0 xb h2 y31 ff1 fs0 fc0 sc0 ls0 ws0">8.2.4.2. </div><div class="t m0 xa hb y32 ff1 fs0 fc0 sc0 ls5 ws0">2. Add programming guidelines about I2S/PCM in Section 8.8.4. </div><div class="t m0 x2 h2 y33 ff1 fs0 fc0 sc0 ls0 ws0"> </div></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div>

<div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/12968428/bg3.jpg"><div class="t m0 x8 h7 y15 ff3 fs4 fc0 sc0 ls0 ws0"> Contents </div><div class="t m0 x2 h8 y16 ff1 fs4 fc0 sc0 ls0 ws0">A40i User Manual(Revision 1.1) Copyright© 2018 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 4 </div><div class="t m0 x2 h2 y34 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xc h9 y35 ff2 fs5 fc0 sc0 ls0 ws0">Contents </div><div class="t m0 x2 h2 y36 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 x2 h2 y37 ff1 fs0 fc0 sc0 ls0 ws0">Declaration ............................................................................................................................................................................ 2 </div><div class="t m0 x2 h2 y38 ff1 fs0 fc0 sc0 ls0 ws0">Revision History..................................................................................................................................................................... 3 </div><div class="t m0 x2 h2 y39 ff1 fs0 fc0 sc0 ls0 ws0">Contents ................................................................................................................................................................................ 4 </div><div class="t m0 x2 h2 y3a ff1 fs0 fc0 sc0 ls0 ws0">Figures ................................................................................................................................................................................. 32 </div><div class="t m0 x2 h2 y3b ff1 fs0 fc0 sc0 ls0 ws0">Tables .................................................................................................................................................................................. 35 </div><div class="t m0 x2 h2 y3c ff1 fs0 fc0 sc0 ls0 ws0">Chapter 1. About This Documentation ............................................................................................................................... 37 </div><div class="t m0 xd h2 y3d ff1 fs0 fc0 sc0 ls0 ws0">1.1. Purpose ................................................................................................................................................................ 37 </div><div class="t m0 xd h2 y3e ff1 fs0 fc0 sc0 ls0 ws0">1.2. Intended Audience ............................................................................................................................................... 37 </div><div class="t m0 xd h2 y3f ff1 fs0 fc0 sc0 ls0 ws0">1.3. Symbol Conventions ............................................................................................................................................. 37 </div><div class="t m0 xd h2 y40 ff1 fs0 fc0 sc0 ls0 ws0">1.4. Notes .................................................................................................................................................................... 37 </div><div class="t m0 xe h2 y41 ff1 fs0 fc0 sc0 ls0 ws0">1.4.1. Register Attributes .................................................................................................................................... 37 </div><div class="t m0 xe h2 y42 ff1 fs0 fc0 sc0 ls0 ws0">1.4.2. Reset Value Conventions ........................................................................................................................... 38 </div><div class="t m0 xe h2 y43 ff1 fs0 fc0 sc0 ls0 ws0">1.4.3. Numerical System...................................................................................................................................... 38 </div><div class="t m0 xd h2 y44 ff1 fs0 fc0 sc0 ls0 ws0">1.5. Acronyms and Abbreviations ............................................................................................................................... 38 </div><div class="t m0 x2 h2 y45 ff1 fs0 fc0 sc0 ls0 ws0">Chapter 2. Overview............................................................................................................................................................ 41 </div><div class="t m0 xd h2 y46 ff1 fs0 fc0 sc0 ls0 ws0">2.1. Processor Overview ............................................................................................................................................. 42 </div><div class="t m0 xd h2 y47 ff1 fs0 fc0 sc0 ls0 ws0">2.2. Features ............................................................................................................................................................... 43 </div><div class="t m0 xe h2 y48 ff1 fs0 fc0 sc0 ls0 ws0">2.2.1. CPU Architecture ....................................................................................................................................... 43 </div><div class="t m0 xe h2 y49 ff1 fs0 fc0 sc0 ls0 ws0">2.2.2. GPU Architecture....................................................................................................................................... 43 </div><div class="t m0 xe h2 y4a ff1 fs0 fc0 sc0 ls0 ws0">2.2.3. Memory ..................................................................................................................................................... 43 </div><div class="t m0 xf h2 y4b ff1 fs0 fc0 sc0 ls0 ws0">2.2.3.1. Boot ROM ....................................................................................................................................... 43 </div><div class="t m0 xf h2 y4c ff1 fs0 fc0 sc0 ls0 ws0">2.2.3.2. SDRAM ........................................................................................................................................... 43 </div><div class="t m0 xf h2 y4d ff1 fs0 fc0 sc0 ls0 ws0">2.2.3.3. NAND Flash..................................................................................................................................... 43 </div><div class="t m0 xf h2 y4e ff1 fs0 fc0 sc0 ls0 ws0">2.2.3.4. SMHC .............................................................................................................................................. 44 </div><div class="t m0 xe h2 y4f ff1 fs0 fc0 sc0 ls0 ws0">2.2.4. System Peripherals .................................................................................................................................... 44 </div><div class="t m0 xf h2 y50 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.1. Timer .............................................................................................................................................. 44 </div><div class="t m0 xf h2 y51 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.2. High Speed Timer ........................................................................................................................... 44 </div><div class="t m0 xf h2 y52 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.3. GIC .................................................................................................................................................. 44 </div><div class="t m0 xf h2 y53 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.4. DMA ............................................................................................................................................... 44 </div><div class="t m0 xf h2 y54 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.5. CCU ................................................................................................................................................. 44 </div><div class="t m0 xf h2 y55 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.6. RTC ................................................................................................................................................. 45 </div><div class="t m0 xf h2 y56 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.7. PWM ............................................................................................................................................... 45 </div><div class="t m0 xf h2 y57 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.8. Thermal Sensor .............................................................................................................................. 45 </div><div class="t m0 xf h2 y58 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.9. Crypto Engine ................................................................................................................................. 45 </div><div class="t m0 xf h2 y59 ff1 fs0 fc0 sc0 ls0 ws0">2.2.4.10. Security ID .................................................................................................................................... 45 </div><div class="t m0 xe h2 y5a ff1 fs0 fc0 sc0 ls0 ws0">2.2.5. Video Engine ............................................................................................................................................. 45 </div><div class="t m0 xf h2 y5b ff1 fs0 fc0 sc0 ls0 ws0">2.2.5.1. Video Decoder ................................................................................................................................ 45 </div><div class="t m0 xf h2 y5c ff1 fs0 fc0 sc0 ls0 ws0">2.2.5.2. Video Encoder ................................................................................................................................ 46 </div><div class="t m0 xe h2 y5d ff1 fs0 fc0 sc0 ls0 ws0">2.2.6. Display Subsystem ..................................................................................................................................... 46 </div><div class="t m0 xf h2 y5e ff1 fs0 fc0 sc0 ls0 ws0">2.2.6.1. DE2.0 .............................................................................................................................................. 46 </div><div class="t m0 xf h2 y5f ff1 fs0 fc0 sc0 ls0 ws0">2.2.6.2. Video Output .................................................................................................................................. 46 </div><div class="t m0 xe h2 y60 ff1 fs0 fc0 sc0 ls0 ws0">2.2.7. Image Subsystem....................................................................................................................................... 46 </div><div class="t m0 xe h2 y61 ff1 fs0 fc0 sc0 ls0 ws0">2.2.8. Analog Subsystem ..................................................................................................................................... 47 </div><div class="t m0 xf h2 y62 ff1 fs0 fc0 sc0 ls0 ws0">2.2.8.1. Analog Codec ................................................................................................................................. 47 </div><div class="t m0 xf h2 y63 ff1 fs0 fc0 sc0 ls0 ws0">2.2.8.2. I2S/PCM .......................................................................................................................................... 47 </div><div class="t m0 xf h2 y64 ff1 fs0 fc0 sc0 ls0 ws0">2.2.8.3. OWA ............................................................................................................................................... 47 </div><div class="t m0 xf h2 y65 ff1 fs0 fc0 sc0 ls0 ws0">2.2.8.4. AC97 ............................................................................................................................................... 48 </div><div class="t m0 xe h2 y66 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9. External Peripherals .................................................................................................................................. 48 </div><div class="t m0 xf h2 y67 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.1. USB ................................................................................................................................................. 48</div><div class="t m0 x10 h2 y68 ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xf h2 y69 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.2. EMAC .............................................................................................................................................. 48 </div><div class="t m0 xf h2 y6a ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.3. GMAC ............................................................................................................................................. 48 </div><div class="d m1"></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div>

<div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/12968428/bg4.jpg"><div class="t m0 x8 h7 y15 ff3 fs4 fc0 sc0 ls0 ws0"> Contents </div><div class="t m0 x2 h8 y16 ff1 fs4 fc0 sc0 ls0 ws0">A40i User Manual(Revision 1.1) Copyright© 2018 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 5 </div><div class="t m0 xf h2 y34 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.4. Transport Stream Controller .......................................................................................................... 48 </div><div class="t m0 xf h2 y6b ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.5. TWI ................................................................................................................................................. 48 </div><div class="t m0 xf h2 y6c ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.6. Smart Card Reader ......................................................................................................................... 49 </div><div class="t m0 xf h2 y6d ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.7. SPI ................................................................................................................................................... 49 </div><div class="t m0 xf h2 y6e ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.8. UART ............................................................................................................................................... 49 </div><div class="t m0 xf h2 y6f ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.9. PS2 .................................................................................................................................................. 49 </div><div class="t m0 xf h2 y70 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.10. CIR ................................................................................................................................................ 49 </div><div class="t m0 xf h2 y71 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.11. SATA ............................................................................................................................................. 50 </div><div class="t m0 xf h2 y72 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.12. Keypad .......................................................................................................................................... 50 </div><div class="t m0 xf h2 y73 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.13. KEYADC ......................................................................................................................................... 50 </div><div class="t m0 xf h2 y74 ff1 fs0 fc0 sc0 ls0 ws0">2.2.9.14. RTP ............................................................................................................................................... 50 </div><div class="t m0 xe h2 y75 ff1 fs0 fc0 sc0 ls0 ws0">2.2.10. Package ................................................................................................................................................... 50 </div><div class="t m0 xd h2 y76 ff1 fs0 fc0 sc0 ls0 ws0">2.3. Block Diagram ...................................................................................................................................................... 51 </div><div class="t m0 x2 h2 y77 ff1 fs0 fc0 sc0 ls0 ws0">Chapter 3. System ............................................................................................................................................................... 53 </div><div class="t m0 xd h2 y78 ff1 fs0 fc0 sc0 ls0 ws0">3.1. Memory Mapping ................................................................................................................................................ 54 </div><div class="t m0 xd h2 y79 ff1 fs0 fc0 sc0 ls0 ws0">3.2. CPU Configuration ................................................................................................................................................ 57 </div><div class="t m0 xe h2 y7a ff1 fs0 fc0 sc0 ls0 ws0">3.2.1. Overview ................................................................................................................................................... 57 </div><div class="t m0 xe h2 y7b ff1 fs0 fc0 sc0 ls0 ws0">3.2.2. Register List ............................................................................................................................................... 57 </div><div class="t m0 xe h2 y7c ff1 fs0 fc0 sc0 ls0 ws0">3.2.3. Register Description .................................................................................................................................. 58 </div><div class="t m0 xf h2 y7d ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.1. CPU0 Reset Control(Default Value: 0x0000_0003) ........................................................................ 58 </div><div class="t m0 xf h2 y7e ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.2. CPU0 Control Register(Default Value: 0x0000_0000) .................................................................... 58 </div><div class="t m0 xf h2 y7f ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.3. CPU0 Status Register(Default Value: 0x0000_0000) ...................................................................... 58 </div><div class="t m0 xf h2 y80 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.4. CPU1 Reset Control(Default Value: 0x0000_0001) ........................................................................ 59 </div><div class="t m0 xf h2 y81 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.5. CPU1 Control Register(Default Value: 0x0000_0000) .................................................................... 59 </div><div class="t m0 xf h2 y82 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.6. CPU1 Status Register(Default Value: 0x0000_0000) ...................................................................... 60 </div><div class="t m0 xf h2 y83 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.7. CPU2 Reset Control(Default Value: 0x0000_0001) ........................................................................ 60 </div><div class="t m0 xf h2 y84 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.8. CPU2 Control Register(Default Value: 0x0000_0000) .................................................................... 60 </div><div class="t m0 xf h2 y85 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.9. CPU2 Status Register(Default Value: 0x0000_0000) ...................................................................... 61 </div><div class="t m0 xf h2 y86 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.10. CPU3 Reset Control(Default Value: 0x0000_0001) ...................................................................... 61 </div><div class="t m0 xf h2 y87 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.11. CPU3 Control Register(Default Value: 0x0000_0000) .................................................................. 61 </div><div class="t m0 xf h2 y88 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.12. CPU3 Status Register(Default Value: 0x0000_0000) .................................................................... 62 </div><div class="t m0 xf h2 y89 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.13. CPUX Power Off Gating Register(Default Value: 0x0000_0000) ................................................... 62 </div><div class="t m0 xf h2 y8a ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.14. CPU0 Power Switch Control Register(Default Value: 0x0000_0000) ............................................ 62 </div><div class="t m0 xf h2 y8b ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.15. CPU1 Power Switch Control Register(Default Value: 0x0000_0000) ............................................ 62 </div><div class="t m0 xf h2 y8c ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.16. CPUIDLE Enable Control Register(Default Value: 0x0000_0000) ................................................. 63</div><div class="t m0 x10 h2 y8d ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xf h2 y8e ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.17. Close Core Flag Register(Default Value: 0x0000_0000) ............................................................... 63 </div><div class="t m0 xf h2 y8f ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.18. IRQ_FIQ Status and Control Register(Default Value: 0x0000_0000) ............................................ 63 </div><div class="t m0 xf h2 y90 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.19. Power Switch Delay Register(Default Value: 0x0000_000A) ........................................................ 64 </div><div class="t m0 xf h2 y91 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.20. Configuration Delay Register(Default Value: 0x0000_0001) ........................................................ 64 </div><div class="t m0 xf h2 y92 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.21. Power Down Configuration Register(Default Value: 0x0000_00FF) ............................................. 64 </div><div class="t m0 xf h2 y93 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.22. Power Up Configuration Register0(Default Value: 0x0000_00FE)................................................ 64 </div><div class="t m0 xf h2 y94 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.23. Power Up Configuration Register1(Default Value: 0x0000_00FC) ............................................... 64 </div><div class="t m0 xf h2 y95 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.24. Power Up Configuration Register2(Default Value: 0x0000_00F8) ............................................... 65 </div><div class="t m0 xf h2 y96 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.25. Power Up Configuration Register3(Default Value: 0x0000_00F0) ............................................... 65 </div><div class="t m0 xf h2 y97 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.26. Power Up Configuration Register4(Default Value: 0x0000_00C0) ............................................... 65 </div><div class="t m0 xf h2 y98 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.27. Power Up Configuration Register5(Default Value: 0x0000_0000) ............................................... 65 </div><div class="t m0 xf h2 y99 ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.28. General Control Register(Default Value: 0x1000_0020) .............................................................. 65 </div><div class="t m0 xf h2 y9a ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.29. Event Input Register(Default Value: 0x0000_0000) ..................................................................... 66 </div><div class="t m0 xf h2 y9b ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.30. 64-bit Counter Control Register(Default Value: 0x0000_0000) ................................................... 66 </div><div class="t m0 xf h2 y9c ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.31. 64-bit Counter Low Register(Default Value: 0x0000_0000) ......................................................... 67 </div><div class="t m0 xf h2 y9d ff1 fs0 fc0 sc0 ls0 ws0">3.2.3.32. 64-bit Counter High Register(Default Value: 0x0000_0000) ........................................................ 67 </div><div class="t m0 xd h2 y9e ff1 fs0 fc0 sc0 ls0 ws0">3.3. CCU ....................................................................................................................................................................... 68 </div><div class="t m0 xe h2 y9f ff1 fs0 fc0 sc0 ls0 ws0">3.3.1. Overview ................................................................................................................................................... 68 </div><div class="t m0 xe h2 ya0 ff1 fs0 fc0 sc0 ls0 ws0">3.3.2. Operations and Functional Descriptions ................................................................................................... 69 </div><div class="t m0 xf h2 ya1 ff1 fs0 fc0 sc0 ls0 ws0">3.3.2.1. Block Diagram ................................................................................................................................ 69 </div><div class="t m0 xf h2 ya2 ff1 fs0 fc0 sc0 ls0 ws0">3.3.2.2. Typical Applications........................................................................................................................ 73 </div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div>

<div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="https://csdnimg.cn/release/download_crawler_static/12968428/bg5.jpg"><div class="t m0 x8 h7 y15 ff3 fs4 fc0 sc0 ls0 ws0"> Contents </div><div class="t m0 x2 h8 y16 ff1 fs4 fc0 sc0 ls0 ws0">A40i User Manual(Revision 1.1) Copyright© 2018 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 6 </div><div class="t m0 xf h2 y34 ff1 fs0 fc0 sc0 ls0 ws0">3.3.2.3. PLL .................................................................................................................................................. 73 </div><div class="t m0 xf h2 y6b ff1 fs0 fc0 sc0 ls0 ws0">3.3.2.4. Bus .................................................................................................................................................. 74 </div><div class="t m0 xf h2 y6c ff1 fs0 fc0 sc0 ls0 ws0">3.3.2.5. Clock Switch ................................................................................................................................... 74 </div><div class="t m0 xf h2 y6d ff1 fs0 fc0 sc0 ls0 ws0">3.3.2.6. Reset and Gating ............................................................................................................................ 74 </div><div class="t m0 xf h2 y6e ff1 fs0 fc0 sc0 ls0 ws0">3.3.2.7. Spread Spectrum Function ............................................................................................................. 74 </div><div class="t m0 xe h2 y6f ff1 fs0 fc0 sc0 ls0 ws0">3.3.3. Register List ............................................................................................................................................... 74 </div><div class="t m0 xe h2 y70 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4. Register Description .................................................................................................................................. 77 </div><div class="t m0 xf h2 y71 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.1. PLL_CPUX Control Register (Default Value: 0x0000_1000) ............................................................ 77 </div><div class="t m0 xf h2 y72 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.2. PLL_AUDIO Control Register (Default Value: 0x000_35514) .......................................................... 78 </div><div class="t m0 xf h2 y73 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.3. PLL_VIDEO0 Control Register (Default Value: 0x0300_6207) ......................................................... 79 </div><div class="t m0 xf h2 y74 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.4. PLL_VE Control Register (Default Value: 0x0300_6207) ................................................................. 80 </div><div class="t m0 xf h2 y75 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.5. PLL_DDR0 Control Register (Default Value: 0x0000_1000) ............................................................ 81 </div><div class="t m0 xf h2 y76 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.6. PLL_PERIPH0 Control Register (Default Value: 0x0004_1811) ....................................................... 81 </div><div class="t m0 xf h2 y77 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.7. PLL_PERIPH1 Control Register (Default Value: 0x0004_1811) ....................................................... 83 </div><div class="t m0 xf h2 y78 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.8. PLL_VIDEO1 Control Register (Default Value: 0x0300_6207) ......................................................... 84 </div><div class="t m0 xf h2 y79 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.9. PLL_SATA Control Register (Default Value: 0x0000_1811) ............................................................. 85 </div><div class="t m0 xf h2 y7a ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.10. PLL_GPU Control Register (Default Value: 0x0300_6207) ............................................................ 86 </div><div class="t m0 xf h2 y7b ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.11. PLL_MIPI Control Register (Default Value: 0x0000_0515) ........................................................... 87 </div><div class="t m0 xf h2 y7c ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.12. PLL_DE Control Register (Default Value: 0x0300_6207) .............................................................. 88 </div><div class="t m0 xf h2 y7d ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.13. PLL_DDR1 Control Register (Default Value: 0x0000_1800) .......................................................... 89 </div><div class="t m0 xf h2 y7e ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.14. CPUX/AXI Configuration Register (Default Value: 0x0001_0300) ................................................ 90 </div><div class="t m0 xf h2 y7f ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.15. AHB1/APB1 Configuration Register (Default Value: 0x0000_1010) .............................................. 90 </div><div class="t m0 xf h2 y80 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.16. APB2 Configuration Register (Default Value: 0x0100_0000) ....................................................... 91 </div><div class="t m0 xf h2 y81 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.17. Bus Clock Gating Register 0 (Default Value: 0x0000_0000) ......................................................... 91 </div><div class="t m0 xf h2 y82 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.18. Bus Clock Gating Register 1 (Default Value: 0x0000_0000) ......................................................... 94 </div><div class="t m0 xf h2 y83 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.19. Bus Clock Gating Register 2 (Default Value: 0x0000_0000) ......................................................... 96 </div><div class="t m0 xf h2 y84 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.20. Bus Clock Gating Register 3 (Default Value: 0x0000_0000) ......................................................... 97 </div><div class="t m0 xf h2 y85 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.21. Bus Clock Gating Register 4 (Default Value: 0x0000_0000) ......................................................... 99 </div><div class="t m0 xf h2 y86 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.22. THS Clock Register (Default Value: 0x0000_0000) ....................................................................... 99 </div><div class="t m0 xf h2 y87 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.23. NAND Clock Register (Default Value: 0x0000_0000) ................................................................. 100 </div><div class="t m0 xf h2 y88 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.24. SMHC0 Clock Register (Default Value: 0x0000_0000)................................................................ 100 </div><div class="t m0 xf h2 y89 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.25. SMHC1 Clock Register (Default Value: 0x0000_0000) ................................................................ 101 </div><div class="t m0 xf h2 y8a ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.26. SMHC2 Clock Register (Default Value: 0x0000_0000) ................................................................ 101 </div><div class="t m0 xf h2 y8b ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.27. SMHC3 Clock Register (Default Value: 0x0000_0000) ................................................................ 102 </div><div class="t m0 xf h2 y8c ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.28. TS Clock Register (Default Value: 0x0000_0000) ........................................................................ 103 </div><div class="t m0 xf h2 ya3 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.29. CE Clock Register (Default Value: 0x0000_0000) ....................................................................... 103 </div><div class="t m0 xf h2 ya4 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.30. SPI0 Clock Register (Default Value: 0x0000_0000) .................................................................... 104 </div><div class="t m0 xf h2 ya5 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.31. SPI1 Clock Register (Default Value: 0x0000_0000) .................................................................... 104 </div><div class="t m0 xf h2 ya6 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.32. SPI2 Clock Register (Default Value: 0x0000_0000) .................................................................... 105 </div><div class="t m0 xf h2 ya7 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.33. SPI3 Clock Register (Default Value: 0x0000_0000) .................................................................... 106 </div><div class="t m0 xf h2 ya8 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.34. I2S/PCM0 Clock Register (Default Value: 0x0000_0000) ........................................................... 106 </div><div class="t m0 xf h2 ya9 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.35. I2S/PCM1 Clock Register (Default Value: 0x0000_0000) ........................................................... 107 </div><div class="t m0 xf h2 yaa ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.36. I2S/PCM2 Clock Register (Default Value: 0x0000_0000) ........................................................... 107 </div><div class="t m0 xf h2 yab ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.37. AC97 Clock Register(Default Value: 0x0003_0000) .................................................................... 107 </div><div class="t m0 xf h2 yac ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.38. OWA Clock Register (Default Value: 0x0001_0000) ................................................................... 108 </div><div class="t m0 xf h2 yad ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.39. KEYPAD Clock Register (Default Value: 0x0000_001F) ............................................................... 108</div><div class="t m0 x10 h2 yae ff1 fs0 fc0 sc0 ls0 ws0"> </div><div class="t m0 xf h2 yaf ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.40. SATA Clock Register (Default Value: 0x0000_0000) .................................................................... 109 </div><div class="t m0 xf h2 yb0 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.41. USBPHY Configuration Register (Default Value: 0x0000_0000) ................................................. 109 </div><div class="t m0 xf h2 yb1 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.42. CIR0 Clock Register (Default Value: 0x0000_0000) .................................................................... 110 </div><div class="t m0 xf h2 yb2 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.43. CIR1 Clock Register (Default Value: 0x0000_0000) .................................................................... 111 </div><div class="t m0 xf h2 yb3 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.44. PLL_DDR Auxiliary Register (Default Value: 0x0000_0001)........................................................ 112 </div><div class="t m0 xf h2 yb4 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.45. DRAM Configuration Register (Default Value: 0x0000_0000) .................................................... 112 </div><div class="t m0 xf h2 yb5 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.46. PLL_DDR1 Configuration Register (Default Value: 0x0CCC_A000) ............................................. 112 </div><div class="t m0 xf h2 yb6 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.47. MBUS Reset Register (Default Value: 0x8000_0000) ................................................................. 113 </div><div class="t m0 xf h2 yb7 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.48. DRAM Clock Gating Register (Default Value: 0x0000_0000) ...................................................... 113 </div><div class="t m0 xf h2 yb8 ff1 fs0 fc0 sc0 ls0 ws0">3.3.4.49. DE Clock Register (Default Value: 0x0000_0000) ....................................................................... 114 </div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div>

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