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The Verilog Hardware Description Language(Verilog hdl) became an ieee standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overw helming number of ic designers Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches, and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in which expressions of both variables and nets can continuously drive values onto nets, provide the basic structural construct Procedural assignments, in which the results of calculations involving variable and net values can be stored into variables, provide the basic behavioral construct. a design consists of a set of mod- ules, each of which has an I/O interface, and a description of its function, which can be structural, behav- ioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets The Verilog language is extensible via the Programming Language Interface(PLI) and the verilog proce dural Interface(VPD)routines. The Pli/VPI is a collection of routines that allows foreign functions to access information contained in a Verilog hdl description of the design and facilitates dynamic interaction with simulation. Applications of PLi/VPi include connecting to a Verilog hdl simulator with other simulation and CAD systems, customized debugging tasks, delay calculators, and annotators The language that influenced Verilog hDL the most was HILo-2, which was developed at Brunel University in England under a contract to produce a test generation system for the british ministry of Defense. HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification simula tion, timing analysis, fault simulation, and test generation In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open Verilog International (OVi)was formed to manage and promote Verilog HDL. In 1992, the Board of direc- tors of oVi began an effort to establish Verilog hdl as an ieee standard. In 1993, the first ieee Working Group was formed and after 18 months of focused efforts verilog became an IEEE standard as ieee Std 1364-1995 After the standardization process was complete the 1364 Working Group started looking for feedback from 1364 users worldwide so the standard could be enhanced and modified accordingly. This led to a five year effort to get a much better Verilog standard in IEEE Std 1364-2001 Objective of the IEEE Std 1364-2001 effort The starting point for the Ieee 13 64 Working Group for this standard was the feedback received from the IFEF Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in all aspects of the language. Users at the higher levels wanted to expand and improve the language at the rtl d behavioral levels, while users at the lower levels wanted improved capability for asiC designs and signoff. It was for this reason that the 1364 Working Group was organized into three task forces: Behavioral ASIC. and Pli The clear directive from the users for these three task forces was to start by solving some of the following problems Consolidate existing IeeE Std 1364-1995 Verilog generate statement Multi-dimensional arrays Enhanced Verilog file I/O Re-entrant tasks Standardize Verilog configurations Enhance timing representation Enhance the vpi routines Achievements Over a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrm The three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of con solidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for the Behavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance- ments that were requested (including the ones stated above) Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configu ration management and has been added to facilitate both the sharing of verilog designs between designers and/or design groups and the repeatability of the exact contents of a given simulation session Clause 15 Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more full how timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format (SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001 Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioral and other areas of the lrm. minimum work has been done on the pli routines and most of the work has been concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu- lation control, work area access, error handling, assign/deassign and support for array of instances, generate and file 1/0 Work on this standard would not have been possible without funding from the cas society of the ieee and Open verilog International The IEEE Std 1364-2001 Verilog standards Group organization Many individuals from many different organizations participated directly or indirectly in the standardization process. The main body of the Ieee Std 1364-2001 working group is located in the United States, with a subgroup in Japan (EIAJ/1364HDL) The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to be approved by this group to be implemented the three task forces focused on their specific areas and their recommendations were eventually voted on by the Ieee Std 1364-2001 working group At the time this document was approved, the TEEf Std 1364-2001 working group had the following embers Kurt baty Adam Krolnik Karen Pieper Stefen boyd James a. markevitch Steven Sharp Shalom bresticker Michael mcnamara Chris Spear Tom Fitzpatrick Anders nordstrom Stuart Sutherland Leigh Brady Ted elkind Marck r Paul colwill Lukasz Tom Dewey Prabhakaran Krishnamurthy Deborah Dalio Steve meyer Girish s rao Charles dawson David roberts The IEEE 1364 Japan subgroup(eiAJ/1364HDL) consisted of the following members Yokozeki atsushi Yasuaki hatta Takashima mitsuya Tsutomu Someya Tatsuro nakamura Verilog is a registered trademark of Cadence Design Systems, Inc

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