Hi3516CV300资料

Hi3516CV300资料 Mainstream Full-HD IP Camera Soc Hi3516CV300 Key features: ARM926@800MHz; 1080P@30fps+720@30fps H.265 MP encoding; Max.2M Pixel sensor input; 2-frame WDR,Tone mapping.
Hi3516CV300 Hi3516C V300 Professional hd ip camera SoC Brief Data sheet Key Specifications Audio 3A functions(AEC, ANR, and Agic) Processor Core Security Engine Various encryption and decryption al gorithms ARM926(a800 MHz with 32 KB I-cachc and 32 KB D-cachc implemented by using hardware, including AEs, DES Video encoding BDES and rsa H. 264 BP/MP/HP e HASH(SHAI/SHA256/HMAC SHA/HMAC SHA256) H265 Main profile algorithms implemented by using hardware MIPEGAIPEG baseline e Integrated 512-bit OTP storage space and random number Video Encoding Performance cinerator e Maximum 2-megapixel resolution for 11.264711.265 Video Interfaces encoding ● VI interfaces Real-time multi-stream H. 264/H 265 encoding capabilities 8-710-12-14-bit RGB Baver dc timing vi 1920X1080@45ips BT 601. BT 656 and BT1120 VI interfaces 1920x1080@30fips+720x48030印ps+360X240@30 MIPL LVDS/Sub-LVDS and HiSPi Compatibility with mainstream HD CMOS sensors JPEG snapshot at 2 megapixels @5 fps provided by Sony, ON, Omni vision, and Panasonic CBR, VBR, FIXQP, AVBR, and QPMAP modes Compatibility with the electrical specifications of Maximum 30 Mbit/s output bit rate parallel and differential interfaces of various sensors Encoding of eight ROls Programmable sensor clock output Intelligent Video analysis Maximum input resolution of 2048 x 2048, up to 198 Integrated IVE, supporting various intelligent analysis applications such as motion detection, perimeter defense, and ● Vo interfaces video diagnosis One Pal/ntSC output for automatic load detection One bt,656 yo interface Video and Graphics Processing 6-bit RGB565 serial LCD output 3DNR, image enhancement, and dCi Audio interfaces e Anti-flicker for output videos and graphics e 1715x to 1 6x video and graphic scaling o Integrated audio CodEC supporting 16-bit audio inputs Overlaying of vidco and graphics and outputs ● Picture rotation by90°,180°or270 Mono-channel differential MIC inputs for reducing the Picture mirroring and flipping background noises OSD overlaying of eight regions before encoding Single-ended dual-channel input e I S interface for connecting to the external audio codeC ISP Peripheral Interfaces 3A(AE, AF, and AWB) function. The third-party 3A ●POR algorithms are supported. ● FPN removal and dpc One integrated high-precision RTC Integrated 3-channel LsadC LSC, LDC and purple edge correction e Direction-adaptive demosaic Three UART interfaces(including one 4-wire interface) e Gamma correction, DCl, and color managcment and IR. IC. SPL and GPio interfaces Four PWm interfaces enhancement Adaptive region de-fo e Two SDIO 2.0 interfaces, supporting the 3.3 V level and Multi-level NR(BayerNR and 3DNR) and sharpening 1. 8V level One uSb 2.0 host/device port ent Local tone mapping RMII in 10/100 Mbit/s full-duplex or half-duplex mode Sensor built-in WDR and 2F WDR (line-base/frame TSO nctwork accclcration, and PhY clock output basc/DCG) External Memory Interfaces DIS SDRAM interface e ISP tuning tools for the pc 16-bit ddr3/ddR3L interfacc with the maximum Audio Encoding/Decoding capacity of 4 (bits Voice encoding/decoding complying with multiple o SPI NOR flash interface 1-/4-wire node protocols by using software Compliance with the G.711, G726, and ADPCM Maximum capacity of 32 MB SPI NAND flash interface with maximum 4 Gbits protocols pacity HiSilicon Proprietary and confidential Issue03(2016-11-10 Copyright C HiSilicon Technologies Co, Ltd Hi3516CV300 Hi3516C V300 Professional hd ip camera SoC Brief Data sheet SD card interface supporting the maximum capacity of 2 Physical specifications ● Power consumption eMMC 4.5 interface with 4-bit data width 1080p.30, typical power consumption of 550 mW Boot Booting from the SPI NOR flash, SPI NAND Mash, or ● Operating voltages eMMC 0.9 V core voltage Secure boot 3.3V±10% I/O voltage SDK 35Vor 15V DDR3/3L SDRAM interface voltage Package Linux-3.18-based SDK Body size of 12 mm x 12 mm(0.47in. x 0. 47 in. ) 0.65 High-performance H. 264 PC decoding library mm(0.03 in ) ball pitch, TFBGA RoHS package with High-performance H265 PC/Android/iOS decodin Functional Block Diagram ARM Subsystem Image subsystem 16bit DDRC Arm926(800MHZ E CVBSA DDR3/DDR3L BT.656 (32K ICache/ RGB565 32K DCache) VPSS+VGS MIPILVDS/ SD/ ISP HiSPi/ eMMC SDIO20 (3A/WDR) BT.1120 SPI NOR Flash /F NAND Flash AMBA3.0 BUS RTC 12CX2 Video subsystem PHY ETH H264/H265 SS SP×3 MJPEGIPEG USB 2.0 Encoder GPIOS USB Host/Device R AESIDESI3DES/HASH UARTX3 Audio ODEC PWMx4 RSA/TRNG LSADCX 3 HR3516CV300 Hi3516C V300 is a new-generation Soc designed for the industry-dedicated HD IP camera. It has an integrated new-generation ISP and the latest H 265 video compression encoder in the industry. It uses the advanced low-power technology and architecture design. All of these features enable Hi3516C v300 to lead the industry in the low bit rate, high profile, and low power consumption Hi3516C V300 integrates thc POR, RIC, audio CoDEC, and standby wakeup circuit, which significantly reduces customcrs'EBOM cost. In addition, the interface design similar to that of other IliSilicon DVR and NVR chips facilitate development and mass production of customer's products HiSilicon Proprietary and confidential Issue03(2016-11-10 Copyright C HiSilicon Technologies Co, Ltd Hi3516CV300 Hi3516C V300 Professional hd ip camera SoC Brief Data sheet Hi3516C v300 HD IP Camera Solution oit DDr DDR3L SPI Flash DDR Aud io codec cvBS- VICAP(ISP) 2M(1080P) CMOS Sensor SPI12C RTC Flash/shutter Photosens itive Hi3516cv300 Cl ADC MAC PHY mdio UARTO/2 UART1 Debug (RS485) ALARM HiSilicon Proprietary and confidential Issue03(2016-11-10 Copyright C HiSilicon Technologies Co, Ltd Hi3516CV300 Hi3516C V300 Professional hd ip camera SoC Brief Data sheet Acronyms and abbreviations 3DES Triple Data Encryption Standard ADPCM adaptive differential pulse code modulation AE automatic exposure AEC acoustic echo cancellation AES Advanced Encryption Standard AF automatic focus ALC automatic level control ANR audio noise reduction AVEr adaptive variable bit rate AWB automatic white balance CBR constant bit rate CMOS complementary metal-oXide-semiconductor CODEC codcr/decoder DC dircct current DCI dynamic contrast improvement DDR double data rate DES Data Encryption Standard DIS digital image stabilization DNR digital noise reduction DPC defect pixel correction DVR digital video recorder EBOM engineering bill of materials embedded multimedia card FPN fixed pattern no GPIO general-purpose input/output HD high definit HiSPi high-speed serial pixel interface C intcr-intcgratcd circuit intcr-IC sound IR HiSilicon Proprietary and confidential Issue03(2016-11-10 Copyright C HiSilicon Technologies Co, Ltd Hi3516CV300 Hi3516C v300 Professional HD IP Camera SoC Brief Data Sheet ISP mage signal processor IVE intelligent video engine LCD liquid crystal display LDC lens distortion correction LSC lens shading correction LVDS low voltage differential signal MIC microphone MIPI mobilc industry processor interface NR noise reduction NTSC National Television System Committee NVR network video recorde OSD on-screen display OTP one-time programmable PAL phase alternating line POR power-on reset PWM pulse-width modulation RMII reduced media independent interface ROHS Restriction of hazardous substances ROI region of interest RSA Rivest-Shamir-Adleman RTC real-time clock SAR ADC successive approximation register analog-to-digital converter SDHO Sccurc Digital High Capacity SDIO sccurc digital input/output SDK software devclopment kit SDRAM synchronous dynamic random access memory SoC system-on-chip SPI serial peripheral interface TFBGA thin fine ball grid array TSO TCP segmentation offload UART universal asynchronous receiver transmitter VBR variable bit rate HiSilicon Proprietary and confidential Issue03(2016-11-10 Copyright C HiSilicon Technologies Co, Ltd Hi3516CV300 Hi3516C V300 Professional hd ip camera SoC Brief Data sheet VGA video graphics array video input VO ideo output WDR wide dynamic range HiSilicon Proprietary and confidential Issue03(2016-11-10 Copyright C HiSilicon Technologies Co, Ltd