Verilog的135个经典设计实例

----------------------- Page 1-----------------------

                                               王金明：《Verilog   HDL 程序设计教程》 

  【例3.1】4 位全加器 

module adder4(cout,sum,ina,inb,cin); 

output[3:0] sum; 

output cout; 

input[3:0] ina,inb; 

input cin; 

assign {cout,sum}=ina+inb+cin; 

endmodule 

  【例3.2】4 位计数器 

module count4(out,reset,clk); 

output[3:0] out; 

input reset,clk; 

reg[3:0] out; 

always @(posedge clk) 

     begin 

     if (reset)  out<=0;              //同步复位 

     else          out<=out+1;       //计数 

     end 

endmodule 

  【例3.3】4 位全加器的仿真程序 

`timescale 1ns/1ns 

`include "adder4.v" 

module adder_tp;                     //测试模块的名字 

reg[3:0] a,b;                        //测试输入信号定义为 reg型 

reg cin; 

wire[3:0] sum;                       //测试输出信号定义为wire型 

wire cout; 

integer i,j;