library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zhong is
port(clk:in std_logic;
rst:in std_logic;
clk1:in std_logic;
md1:in std_logic;
md2:in std_logic_vector(1 downto 0);
speak:out std_logic;
dout:out std_logic_vector(6 downto 0);
selout:out std_logic_vector(2 downto 0));
end zhong;
architecture one of zhong is
signal sel:std_logic_vector(2 downto 0);
signal hou1:std_logic_vector(3 downto 0);
signal hou2:std_logic_vector(3 downto 0);
signal min1:std_logic_vector(3 downto 0);
signal min2:std_logic_vector(3 downto 0);
signal seth1:std_logic_vector(3 downto 0);
signal seth2:std_logic_vector(3 downto 0);
signal setm1:std_logic_vector(3 downto 0);
signal setm2:std_logic_vector(3 downto 0);
signal sec1:std_logic_vector(3 downto 0);
signal sec2:std_logic_vector(3 downto 0);
signal h1:std_logic_vector(3 downto 0);
signal h2:std_logic_vector(3 downto 0);
signal m1:std_logic_vector(3 downto 0);
signal m2:std_logic_vector(3 downto 0);
signal s1:std_logic_vector(3 downto 0);
signal s2:std_logic_vector(3 downto 0);
-------------------------------------------------
begin
----------------------------------------------模6计数
choice:process(clk1)
begin
if clk1'event and clk1='1' then
if sel="101" then
sel<="000";
else
sel<=sel+1;
end if;
end if;
end process choice;
-----------------------------------------------小时十位
h110:process(clk,hou2,min1,min2,sec1,sec2,md1,md2)
begin
if clk'event and clk='1' then
if (hou1="0010" and hou2="0011")and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001") then
hou1<="0000";
elsif hou1="0010"and hou2="0011"and md1='0' and md2="01" then--当时间为23点且处于校时状态时
hou1<="0000";
elsif (hou2="1001"and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001"))or (hou2="1001"and md1='0' and md2="01") then
hou1<=hou1+1;
end if;
end if;
end process h110;
-----------------------------------------------小时个位
h220:process(clk,min1,min2,sec1,sec2,md1,md2,hou1)
begin
