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C8051_C2接口说明
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2010-12-21
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本文为英文,主要介绍了C2接口协议在C8051单片机中的使用说明,另带有编程器的代码 FLASH PROGRAMMING VIA THE C2 INTERFACE
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Rev. 1.1 12/03 Copyright © 2003 by Silicon Laboratories AN127-DS11
AN127
FLASH PROGRAMMING VIA THE C2 INTERFACE
Relevant Devices
This application note applies to the following devices:
C8051F300, C8051F301, C8051F302, and
C8051F303.
Introduction
This application note describes how to program the
FLASH memory on C8051F30x devices through
the C2 interface. Example software is included.
C8051F30x devices have a FLASH Programming
interface (FPI) that is accessed via the C2 Interface
(C2I) and a set of programming registers. The
FLASH access block diagram is shown in Figure 1.
The information needed to access the FLASH
memory via the C2 Interface can be divided into
the three sections listed below.
1. C2 Interface: This includes information about
the C2 physical layer protocol, C2 registers,
and C2 primitive commands.
a. The 2-wire C2 interface (C2CK and
C2D)
b. C2 Address register and its access com-
mands (Address Write, Address Read)
c. C2 Data register access commands
(Data Write, Data Read)
d. Device ID and Revision ID registers
2. FLASH Programming Registers: This
includes the functions of the FLASH Program-
ming registers.
a. FLASH Control register (FPCTL)
b. FLASH Data register (FPDAT)
3. FLASH Programming Interface: This
includes the FLASH Programming Interface
(FPI) commands and procedures.
a. FLASH Block Write
b. FLASH Block Read
c. FLASH Page Erase
d. FLASH User Space Erase
C2 Interface
The C2 Interface (C2I) consists of an Address reg-
ister and access to up to 256 Data registers. Access
to these registers is provided by the C2 physical
layer protocol. For details on the C2 protocol, see
the C2 Specification on the Silicon Labs Applica-
tions website (http://www.silabs.com
).
This application note assumes a basic understand-
ing of the C2 physical layer protocol and the proce-
dure for accessing the C2 Address and Data
registers.
FLASH
Programming
Interface
(FPI)
C2 Interface
(C2I)
FLASH
Programming
Control Register
FLASH
Programming
Data Register
C2CK
C2D
Target Device
Figure 1. C2 FLASH Programming
Architecture
AN127
2 Rev. 1.1
C2 Address Register
The C2 Address register (ADDRESS) serves two
purposes in C2 FLASH programming:
1. ADDRESS selects which C2 Data register is
accessed during C2 Data Read/Write frames
2. During Address Read frames, ADDRESS pro-
vides FPI status information.
Address Reads are used frequently during C2
FLASH programming as a handshaking scheme
between the programmer and the FPI.
The Address Read command returns an 8-bit status
code, formatted as shown in Table 1 .
InBusy should be polled following any write to
FPDAT; OutReady should be polled before any
reads of FPDAT.
DEVICEID: Device ID Register
The Device ID register (DEVICEID) is a read-only
C2 Data register containing the 8-bit device identi-
fier of the target C2 device. The C2 address for reg-
ister DEVICEID is 0x01. The Device ID for all
C8051F30x devices is 0x04.
REVID: Revision ID Register
The Revision ID register (REVID) is a read-only
C2 Data register containing the 8-bit revision iden-
tifier of the target C2 device. The C2 address for
register REVID is 0x01.
Table 1. C2 Address Register Status Bits
Bit Description
7-2 Unused
1
InBusy: This bit is set to ‘1’ by the
C2 Interface following a write to
FPDAT. It is cleared to ‘0’ when the
FPI acknowledges the write to
FPDAT.
0
OutReady: This bit is set to ‘1’ by
the FPI when output data is avail-
able in the FPDAT register.
AN127
Rev. 1.1 3
FLASH Programming
Registers
Communication between the FPI and C2I is
accomplished via two FLASH Programming regis-
ters: FPCTL and FPDAT.
FPCTL: FLASH Programming
Control Register
The FLASH Programming Control register
(FPCTL) serves to enable C2 FLASH program-
ming.
To enable C2 FLASH programming, the following
key codes must be written to FPCTL in the follow-
ing sequence:
1. 0x02
2. 0x01
The key codes must be written in this sequence fol-
lowing a target device reset. Once the key codes
have been written to FPCTL, the target device is
halted until the next device reset.
FPDAT: FLASH Programming
Data Register
The FLASH Programming Data register (FPDAT)
is used to pass all data between the C2I and FPI.
Information passed via FPDAT includes:
1. All FPI Commands (C2I-to-FPI)
2. FPI Status Information (FPI-to-C2I)
3. FLASH Addresses (C2I-to-FPI)
4. FLASH Data (both directions)
Table 2. FLASH Programming Registers
Register C2 Address
FPCTL 0x02
FPDAT 0xB4
AN127
4 Rev. 1.1
FLASH Programming
Interface
The FLASH Programming Interface (FPI) per-
forms a set of four programming commands. Each
command is executed using a sequence of reads
and writes of the FPDAT register. The four FPI
commands are listed in Table 3 .
Before performing any FPI commands, the FPI
must be initialized with the following sequence:
1. Reset the target device.
2. Wait at least 2 µs.
3. Write the following key codes to FPCTL: 0x02,
0x01.
4. Wait at least 20 ms.
The FLASH Programming initialization sequence
is shown in Figure 2.
Table 3. C2 FLASH Programming Commands
Command Code
FLASH Block Write 0x07
FLASH Block Read 0x06
FLASH Page Erase 0x08
Device Erase 0x03
Drive C2CK low
(C2CK = '0')
Wait at least 2 us
Write 0x02 to
FPCTL
Write 0x01 to
FPCTL
Wait at least
20 ms
Wait at least 20 us
Drive C2CK high
(C2CK = '1')
Reset Target
Device
Enable FLASH
Programming
Figure 2. FPI Initialization Sequence
AN127
Rev. 1.1 5
Writing a FLASH Block
All FLASH writes are performed with the FLASH Block Write command. The size of the FLASH block
can be 1-to-256 bytes, and is user-defined during the Block Write sequence. The 8-bit Data Length Code
is formatted as follows:
For (1 ≤ Length Code ≤ 255),
Block Size (in bytes) = Length Code
For (Length Code == 0),
Block Size (in bytes) = 256
The FLASH Block Write sequence is shown in Figure 3. This flow diagram assumes the FPI has been ini-
tialized by following the sequence in Figure 2.
Write Data Byte
1. Write Data to FPDAT
2. Poll for InBusy => '0'
3. Repeat up to 255 times (as
specified by Length code)
Read FPI Command
Status
1. Poll for OutReady => '1'
2. Read Status from FPDAT
3. Abort if Status != 0x0D
Write Data Length Code
(bytes)
1. Write 1-byte Length code to
FPDAT
2. Poll for InBusy => '0'
Write FLASH Address
Low Byte
1. Write Address byte to
FPDAT
2. Poll for InBusy => '0'
Write FLASH Address
High Byte
1. Write Address byte to
FPDAT
2. Poll for InBusy => '0'
Read FPI Command
Status
1. Poll for OutReady => '1'
2. Read Status from FPDAT
3. Abort if Status != 0x0D
Send Write Block
Command
1. Write 0x07 to FPDAT
2. Poll for InBusy => '0'
Figure 3. FLASH Block Write Sequence
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