N 整数分频器verilog

module div_N (
      input CLK,  // 基准时钟
     output CLK_div_N // N分频后得到的时钟
    );
wire [31:0] N=20; // ★ N为分频系数,N≥2即可,N的值为CLK除以CLK_div_N后取整(四舍五入)

 /******************** 产生备用时钟1 ***************/
 reg [31:0] cnt1;
 reg   CLK_div_N_1;
 always @ (posedge CLK)
 begin  
 if(N[0]==0) // 如果N为偶数，比N%2==0这种判断方式更节省资源
  begin
    if(N==2) // 如果N为2
     CLK_div_N_1 <= ~CLK_div_N_1;
    else
     begin
      if(cnt1==((N-2)>>1))   //比cnt1==(N-2)/2这种判断方式更节省资源
      begin
        cnt1 <= 0;
        CLK_div_N_1 <= ~CLK_div_N_1;
       end
      else
       cnt1 <= cnt1+1;
     end
   end
 else // 如果N为奇数
  begin
    if(cnt1==N-1)
     cnt1 <= 0;