loginid=jiangkejun@cmdc.chinamobile.com,time=2022-03-17 19:11:18,ip=120.229.34.168,doctitle=MT7981 Application Note-V1.5_20220310.pdf,company=
MT7981B HW Application Note
Table of Contents
MT7981B MediaTek proprietary and confidential Page 5 of 76
Table of Figures
FIG 4-1 : THE DRAM REFERENCE REGISTERS .......................................................................................................... 9
FIG 4-2 : THE CAPACITORS OF DRAM VREF .......................................................................................................... 10
FIG 4-3 : USB2_1/USB3 ......................................................................................................................................... 10
FIG 4-4 : U3+HSGMII POWER CAPS....................................................................................................................... 12
FIG 4-5 : DRAM CONTROLLER AND DRAM POWER CAP ....................................................................................... 13
FIG 4-6 : VCCK POWER CAPS ................................................................................................................................. 13
FIG 4-7 : MT7981B + MT7976C POWER PLAN (EXAMPLE).................................................................................... 14
FIG 4-8 : MT7981B POWER ON SEQUENCE .......................................................................................................... 15
FIG 4-9 : RESET CIRCUIT ........................................................................................................................................ 15
FIG 4-10 : MT7981B STRAPPING OPTION ............................................................................................................. 17
FIG 4-11 : MT7981B JTAG ..................................................................................................................................... 18
FIG 4-12 : TXAUS FOR THERMAL SENSOR ............................................................................................................. 19
FIG 4-13 : PLLGP_TP/TN (INTERNAL DEBUG PINS) ............................................................................................... 19
FIG 4-14 : TOP_CLK/HB0/HB0_B SIGNAL DESIGN ................................................................................................. 20
FIG 4-15 : AFE POWER CAP ................................................................................................................................... 20
FIG 4-16 : AIQ DESIGN GUIDELINE ........................................................................................................................ 21
FIG 4-17 : SOLUTION FOR WIFI RX DESENSE BY SGMII INTERFERENCE ................................................................ 22
FIG 4-18 : VQPS PIN SHOULD BE CONNECTED TO GND ........................................................................................ 23
FIG 4-19 : MT7981B RFB TOP VIEW ...................................................................................................................... 24
FIG 4-20 : MT7981B REFLOW PROFILE ................................................................................................................. 25
FIG 4-21 : DDR SOC AND DRAM POWER CAP PLACEMENT .................................................................................. 26
FIG 4-22 : USB3.0/USB2.0 LAYOUT NOTICE .......................................................................................................... 27
FIG 4-23 : MT7981 HSGMII LAYOUT GUIDELINE ................................................................................................... 29
FIG 4-24 : THE SHIELDING LINE EXAMPLE OF ETHERNET LAYOUT ........................................................................ 30
FIG 4-25 : THE POWER DEIGN OF MT7981B. ........................................................................................................ 31
FIG 4-26 : THE VCCK CORE FEEDBACK PIN LAYOUT GUIDELINES. ......................................................................... 32
FIG 4-27 : MT7976 RF TRACE LAYOUT GUIDELINE ................................................................................................ 36
FIG 4-28 : IPA/ILNA RF MATCHING ....................................................................................................................... 37
FIG 4-29 : THE G-BAND/A BAND A DIE AIQ LAYOUT ............................................................................................ 38
FIG 4-30 : WF0 HB0/HB0_B IS CLK KEEP OTHER SIGNAL AWAY .......................................................................... 39
FIG 4-31 : PA AVDD33 POWER DE-CAP PLACEMEN ............................................................................................. 40
FIG 4-32 : GND CONNECTION .............................................................................................................................. 41
FIG 4-33 : THERMAL VIA ...................................................................................................................................... 42
FIG 4-34 : MT7976 XTAL TRACE ........................................................................................................................... 43
FIG 4-35 : MT7976 POWER TRACE ROUTING RULE ............................................................................................. 44
FIG 4-36 : MT7976 5G PA POWER TRACE ROUTING RULE .................................................................................... 45
FIG 4-37 : MT7976 1.8V POWER TRACE ROUTING RULE ...................................................................................... 46
FIG 4-38 : MT7976 BAND-GAP PIN ISOLATE ........................................................................................................ 47
FIG 4-39 : SHIELDING FRAME ............................................................................................................................... 48
FIG 4-40 : CRYSTAL LAYOUT GUIDELINES ............................................................................................................. 48
FIG 4-41 : OSC GUIDELINES ................................................................................................................................... 49
FIG 4-42 : SPI FLASH LAYOUT GUIDELINES............................................................................................................ 49
FIG 4-43 : EMMC NAND SCH/PCB DEIGN.............................................................................................................. 50
FIG 5-1 : SGMII TX ELECTRICAL TEST ENVIRONMENT SETUP DIAGRAM ............................................................... 58
