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Connect/Ahstract ConcreteConfigDB l18 Configuring a Test Environment 126 Configuration 126 Resources/config db Config/Params Package 134 Config/Configuring Sequences 139 Resource Access For sequences 142 Macro Cost benefit 145 Analysis Components techniques 146 Analysis l46 Analysis Port Analysis connections 152 Monitor component 158 Predictors 16l Scoreboar 163 MetricAnalyzers 170 Postrunphases 172 Matlab/Integration 175 End of Test mechanisms Endoftest l83 Objections 185 Sequences 188 Sequences 188 Sequences/Items 193 Transaction/methods 195 Sequences/API 200 Connect/Sequencer 204 Driver/Sequence APl 206 quences/generation Sequences/Overrides 221 Sequences/virtual 223 Sequences/virtualsequencer 231 Sequences/Hierarchy 237 Sequences/Sequencelibra 242 Driver/Use models Driver/Unidirectional 17 Driver/Bidirectional 250 Driver/Pipelined Sequences/Arbitration 267 Sequences/Priority 276 Sequences/Lock Grab 277 Sequences/Slave 284 Stimulus/signal wait 290 Stimulus/interrupts 294 Sequences/Stopping Sequences/layering Register abstraction layer 308 Registe 308 Registers/Specification 315 Registers/ Adapter 317 Registers/Integrating 321 Registers/ntegration Registers/RegisterModelOverview 3 Registers/ Modelstructu 334 Registers/Quirkyregist Registers/ModelCoverage 49 Registers/BackdoorAccess 354 Registers/ generation 357 Registers/Stimulus Abstraction 358 Registers/Memory Stimulus 370 Registers/ SequenceExamples 375 Registers/ BuiltInSequences 382 Registers/Configuration Registers/Scoreboarding 389 Registers/ Functionalcoverage 395 Testbench Acceleration through Co-Emulation 401 Emulation 401 Emulation/Separate TopLevel Emulation/Splittransactors 410 Emulation /back pointers 415 Emulation/DefiningAPl 419 Emulation/Example 422 Emulation/Example/APB Driver 430 Emulation/Example/sPlagent 435 Emulation/Example/TopLevel 441 Debug of sv and UVM 444 BuiltIn Debug 444 Reporting/verbosity 455 UVM/CommandLine processor 460 UVM Connect-SV-SystemC interoperability 464 Uvm Connect 464 Uvm Connect/Connections 466 Uvm Connect/Conversion 468 Uvm Connect/CommandAPI 472 UVM Express- step by step improvement 476 UvmExpress 476 UvmExpress/dUT 481 Uvm Express/BFM 485 UvmExpress/Writing BfmTests 490 UvmExpress/Functional Coverage 498 Uvm Express/Constrained random 503 Appendix -Deployment 516 OVM2UVM 516 OVM2U VM/DeprecatedCode 527 OVM2UVM/SequenceLibrary 528 OVM2UVM/Phasing 530 OVMZUVM/Convert Phase Methods UVC/Uvm Verification Component 537 Package/Organization 548 Appendix -Coding Guidelines SV/Guidelines 55 UⅤ M/Guidelines 569 Appendix -Glossary of Te erms 579 Doc/Glossary 57 Datestamp This document is a snapshot of dynamic content from the Online Methodology Cookbook Createdfromhttp://verificationacademy.com/uvm-ovmonWed,04Sep201309:48:38utC 0 Introduction Cookbook/Introduction Universal Verification Methodology (UVm) The Accellera UVM standard was built on the principle of cooperation between EDA vendors and customers; this was made possible by the strong foundation of knowledge and experience that was donated to the standardization effort in the form of the existing ovm code base and contributions from Vmm The result is a hybrid of technologies that originated in Mentor's avm, Mentor Cadence's ovm, verisity's eRM, and Synopsys'S VMM-RAL, tried and tested with our respective customers, along with several new technologies such as Resources, TLM2 and Phasing, all developed by Mentor and others to form UVM as we know it. Combined, these features provide a powerful, flexible technology and methodology to help you create scalable, reusable and interoperable testbenches. With the ovm at its core, the UVM already embodies years of object-oriented design and methodology experience, all of which can be applied immediately to a UVM project When we commenced work on UVM, Mentor set out to capture documentation of our existing OVM methodology at a fine level of granularity. In the process, we realized that learning a new library and methodology needed to be a dynamic and interactive experience, preferably consumed in small, easily digested spoonfuls. To reinforce each UVM and OVM concept or best practice, we developed many realistic, focused code examples. The end result is the UVM/OVM Online Methodology Cookbook, whose recipes can be adapted and applied in many different ways by our field experts, customers, and partners alike The book you are holding contains excerpts from this online resource, covering many aspects of the UVM and OVm Check out our UVM website to learn much more and join others in finding out how you can leverage the uvm in your specific applications Findusonlineathttp://verificationacademy.com/cookbook Uvm/ovMDocumentation-copyright(c)2012MentorGraphicsCorporation-http://verificationacademy.com/uvm-ovm Cookbook/Acknowledgements Cookbook/Acknowledgements UVM/OVM Cookbook authors Gordon Allan Mike baird Rich edelman Adam erickson Michael horn · Mark pryer Adam rose Kurt schwartz We acknowledge the valuable contributions of all our extended team of contributors and reviewers, and those who help deploy our methodology ideas to our customers, including: Alain Goner, Allan Crone, Bahaa Osman, Dave rich, Eric Horton, Gehan Mostafa, Graeme Jessiman, Hans van der Schoot, Hager Fathy, Jennifer Adams, John Carroll, John Amouroux, Jason Polychronopoulos, John Stickley, Nigel Elliot, Peet James, Ray Salemi, Shashi Bhutada, Tim Corcoran and Tom Fitzpatrick Uvm/ovMDocumentation-copyright(c)2012MentorGraphicsCorporation-http://verificationacademy.com/uvm-ovm Testbench architecture Testbench This chapter covers the basics and details of uVm testbench architecture, construction and leads into other chapters covering each of the constituent parts of a typical UVM testbench Testbench Chapter contents Testbench(this page)-top-level introduction into testbench architecture UVM-style Testbench/Build -testbench hierarchy construction in the UVM build phase Testbench/Blocklevel -architecture of a unit-level uvm test environment Testbench/IntegrationLevel-example architecture of vertical reuse testbench gent - architecture of a single interface agent UVM Phases-execution phases in an UVM testbench component UVM Factory -machinery for manufacture of configurable objects Topic overview How an uVm testbench differs from a traditional module based testbench In Verilog or VHDL, a testbench consists of a hierarchy of modules containing testbench code that are connected to the design under test (DUT). The modules contain stimulus and response checking code which is loaded into simulator memory along with the dut at the beginning of the simulation and is present for the duration of the simulation Therefore, the classic Verilog testbench wrapped around a dut consists of what are known as static objects System Verilog builds on top of verilog by adding abstract language constructs targetted at helping the verification process. One of the key additions to the language was the class. System Verilog classes allow Object Orientated Programming(OoP)techniques to be applied to testbenches The UVM itself is a library of base classes which facilitate the creation of structured testbenches using code which is open source and can be run on any System Verilog IEEE 1800 simulator Like classes in any other OOP language such as C++ and Java, System Verilog class definitions are templates for an object that is constructed in memory. Once created, that object persists in memory until it is de-referenced and garbage collected by an automatic background process. The class template defines the members of the class which can either be data variables or methods. In System Verilog, the methods can either be functions which are non-time consuming, or tasks which can consume time. Since a class object has to be constructed before it exists in memory the creation of a class hierarchy in a System Verilog testbench has to be initiated from a module since a module is a static object that is present at the beginning of the simulation. For the same reason, a class cannot contain a module. Classes are referred to as dynamic objects because they can come and go during the life time of a simulation //Example to show how a class is constructed from within a static object (a module) Uvm/ovMDocumentation-copyright(c)2012MentorGraphicsCorporation-http://verificationacademy.com/uvm-ovm Testbench // Example class that contains a message and some convenience methods lass example string messagei function void set_message(string ip__string)i message irstring endfanction: set message function void princ ()i display essage) endfanction: print dcl // Module that uses the class class is constructed, used and dereferenced // i the initial block, after the simulation starts module thi example C;// Null handle after elaboration initial begin C= new()i// Handle points to c object in memory C se- message("This object has been created")i #10; C. print ()i C=nulli //C has been dereferenced, object can be garbage collected ndmodule tr Uvm/ovMDocumentation-copyright(c)2012MentorGraphicsCorporation-http://verificationacademy.com/uvm-ovm

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