System Verilog for Verification, 2nd Edition.pdf

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System Verilog for Verification, 2nd Edition英文版。Chris Spear著。如何使用System Verilog进行验证。
Chris spear System Verilog for Verification A Guide to learning the testbench Language Features Second edition S ringer Chris spear Synopsys, Inc Marlboro. MA USA Library of Congress Control Number: 2008920031 ISBN978-0-387-76529-7 e-ISBN978-0-387-76530-3 Printed on acid-free paper C2008 Springer Science+ Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher(Springer Science+ Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or heareafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights While the advice and information in this book are believed to be true and accurate at the date of going to press, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein springer. com This book is dedicated to my wonderful wife laura, whose patience during this project was invaluable, and my children, Allie and Tyler, who kept me laughing. Contents List of Examples XIll List of figures XXV List of tables XXV Preface XXI Acknowledgments XXXV 1. VERIFICATION GUIDELINES 1.1 The Verification process 2 1. 2 The Verification Methodology Manual 4 1. 3 Basic Testbench Functionality 1. 4 Directed Testing 1. 5 Methodology basics 7 6 Constrained-Random stimulus 8 1. 7 What Should You randomize? 10 1. 8 Functional Coverage 13 1.9 Testbench Components 14 1.10 Layered Testbench 15 Building a Layered Testbench 21 12 Simulation environment phases 22 1.13 Maximum Code Reuse 23 1. 14 Testbench Performance 23 1. 15 Conclusion 24 DATA TYPES 25 2.1 Built-In Data Ty 25 2.2 Fixed-Size Arrays 2.3 Dynamic arrays 34 2. 4 Queues 2.5 Associative Al Contents 2.6 Linked Lists 2. 7 Array Methods 41 2.8 Choosing a Storage Type 46 2.9 Creating New Types with typedef 48 2. 10 Creating User-Defined Structures 50 2.11 Type conversion 52 2. 12 Enumerated Types 2.13 Constants 59 2.14 Str gs 59 2.15 Expression Width 60 2.16 Conclusion 61 3. PROCEDURAL STATEMENTS AND ROUTINES 3.1 Procedural Statements 3.2 Tasks. Functions. and Void Functions 3.3 Task and Function overview 65 3.4 Routine arguments 3.5 Returning from a routine 3.6 Local Data Storage 3.7 Time Values 75 3. 8 Conclusion 77 4. CONNECTING THE TESTBENCH AND DESIGN 4.1 Separating the Testbench and Design 80 4.2 The Interface Construct 82 4.3 Stimulus Timing 88 4.4 Interface Driving and Sampling 96 4.5 Connecting It All Together 103 4.6 Top-Level Scope 104 4.7 Program- Module Interactions 106 4.8 System Verilog Assertions 107 4.9 The Four-Port ATm router 109 4.10 The ref port Direction 117 4.11 The End of simulation l18 412 Directed Test for the lc3 fetch block l18 4.13 Conclusion 124 5. BASIC OOP 125 5.1 Introduction 125 5.2 Think of nouns not verbs 126 5.3 Your First Class 126 Contents 5.4 Where to Define a class 127 5.5 OOP Terminology 128 5.6 Creating New Objects 129 5.7 Object Deallocation 132 5.8 USing Objects 134 5.9 Static Variables vs Global Variables 134 5.10 Class methods 138 5.11 Defining Methods Outside of the Class 139 5. 12 Scoping rules 141 5.13 USing One Class Inside Another 144 5.14 Understanding Dynamic Objects 147 5.15 Copying Objects 151 5.16 Public vs. Local 157 5. 17 Straying Off Course 157 5. 18 Building a Testbench 158 5. 19 Conclusion 159 6. RANDOMIZATION 161 6.1 Introduction 161 6.2 What to randomize 162 6.3 Randomization in System Verilog 165 6.4 Constraint detail 167 6.5 Solution probabilities 178 6.6 Controlling Multiple Constraint Blocks 6.7 Valid Constraints 18 6.8 In-line Constraints 184 The pre randomize and post randomize functions 185 6.10 Random Number functions 187 6. 11 Constraints Tips and Techniques 187 6.12 Common Randomization problems 193 6. 13 Iterative and array constraints 195 6.14 Atomic Stimulus generation vs. Scenario generation 204 6.15 Random Control 207 6.16 Random Number generators 6. 17 Random Device configuration 6.18 Conclusion 216 7. THREADS AND INTERPROCESS COMMUNICATION 217 7.1 Working with Threads 218 7.2 Disabling Threads 228 7.3 Interprocess Communication 232 7. 4 Events 233 7.5 Semaphores 238 7.6 Mailboxes 240 Contents 7.7 Building a Testbench with Threads and IPC 253 7. 8 Conclusion 257 8. ADVANCED OOP AND TESTBENCH GUIDELINES 259 8.1 Introduction to Inheritance 260 8.2 Blueprint Pattern 265 8. 3 Downcasting and virtual methods 270 8.4 Composition, Inheritance, and Alternatives 8.5 Copying an object 279 8.6 Abstract Classes and pure virtual methods 282 8.7 Callbacks 284 8. 8 Parameterized Classes 290 8. 9 Conclusion 9. FUNCTIONAL COVERAGE 295 9.1 Coverage Types 298 9.2 Functional Coverage Strategies 301 9.3 Simple Functional Coverage Example 303 9. 4 Anatomy of a Cover Group 305 9.5 Triggering a Cover Group 307 9.6 Data Sampling 310 9.7 Cross Coverage 319 9.8 Generic Cover Groups 325 9.9 Coverage Options 327 9.10 Analyzing Coverage Data 329 9. 11 Measuring Coverage Statistics During Simulation 331 9.12 Conclusion 332 10. ADVANCED INTERFACES 333 10.1 Virtual Interfaces with the atm router 334 10.2 Connecting to Multiple design Configurations 342 10.3 Procedural Code in an Interface 347 10.4 Conclusion 350 1. A COMPLETE SYSTEMVERILOG TESTBENCH 351 11. 1 Design Blocks 351 11.2 Testbench blocks 356 11. 3 Alternate Tests 377 11. 4 Conclusion 379 12. INTERFACING WITH C 381 12.1 Passing Simple values 382 Contents 12.2 Connecting to a Simple C routine 385 12.3 Connecting to C++ 393 12.4 Simple Array Sharing 398 12.5O pen arrays 12.6 Sharing Composite Types 404 12.7 Pure and Context Imported methods 407 12.8 Communicating from C to System Verilog 407 12.9 Connecting Other Languages 418 12.10 Conclusion 419 References 421 Index 423

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