library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY xuehao IS
PORT(clk:in std_logic;
a,b,c,d,e,f,g,dp:out std_logic;
test:out std_logic_vector(5 downto 0));
END ENTITY;
ARCHITECTURE rtl OF xuehao IS
SIGNAL jishu:std_logic_vector(3 downto 0);
SIGNAL fenpinjishu:std_logic_vecto1001729314359617r(9 downto 0);
SIGNAL gundongjishu:std_logic_vector(23 downto 0);
SIGNAL fenshi:std_logic_vector(2 downto 0);
BEGIN
PROCESS(clk)IS
BEGIN
IF(clk'EVENT AND clk='1') THEN
fenpinjishu<=fenpinjishu + '1';
gundongjishu<=gundongjishu + '1';
IF(fenpinjishu = "1111111111") THEN
fenpinjishu<="0000000000";
jishu<=jishu + '1';
IF(jishu = "0110") THEN
jishu<="0000";
END IF;
END IF;
IF(gundongjishu = "111111111111111111111111") THEN
gundongjishu<="000000000000000000000000";
fenshi<=fenshi + '1';
IF(fenshi = "110") THEN
fenshi<="000";
END IF;
END IF;
END IF;
IF(fenshi = "000") THEN
CASE jishu IS
WHEN
"0000"=>a<='0';b<='0';c<='1';d<='0';e<='0';f<='1';g<='0';dp<='1';test<="011111";
WHEN
"0001"=>a<='0';b<='0';c<='0';d<='0';e<='0';f<='0';g<='1';dp<='1';test<="101111";
