FPGA可编程逻辑器件芯片XC17128DJI中文规格书 fpga开发.pdf
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Chapter3:AboutDesignElements
FDDR
Macro:DualEdgeTriggeredDFlip-FlopwithSynchronousReset
SupportedArchitectures
Thisdesignelementissupportedinthefollowingarchitectures:
CoolRunner™-II
Introduction
ThisdesignelementisasingledualedgetriggeredD-typeip-opwithdata(D)andsynchronousreset(R)
inputsanddataoutput(Q).Thesynchronousreset(R)input,whenHigh,overridesallotherinputsandresetsthe
QoutputLowontheLow-to-HighandHigh-to-Lowclock(C)transitions.ThedataontheDinputisloadedinto
theip-opwhenRisLowduringtheLow-to-HighorHigh-to-Lowclocktransitions.
Thisip-opisasynchronouslycleared,outputsLow,whenpowerisapplied.ForCPLDdevices,youcan
simulatepower-onbyapplyingaHigh-levelpulseonthePRLDglobalnet.
LogicTable
InputsOutputs
RDCQ
1
X
↑
0
1
X
↓
0
01
↑
1
00
↑
0
01
↓
1
00
↓
0
DesignEntryMethod
Thisdesignelementisonlyforuseinschematics.
AvailableAttributes
Attribute
Data
Type
Allowed
ValuesDefaultDescription
INITBinary0,10
SetstheinitialvalueofQoutputafterconguration
CPLDLibrariesGuide
UG606(v14.7)October2,2013
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