GigaDevice Semiconductor Inc.
GD32F3x0
ARM
®
Cortex
™
-M4 32-bit MCU
User Manual
Revision 2.1
(Mar. 2020)
GD32F3x0 User Manual
2
Table of Contents
Table of Contents ........................................................................................................... 2
List of Figures .............................................................................................................. 16
List of Table .................................................................................................................. 23
1. System and memory architecture ........................................................................ 25
1.1. ARM Cortex-M4 processor .............................................................................................. 25
1.2. System architecture ......................................................................................................... 26
1.3. Memory map ...................................................................................................................... 27
1.3.1. Bit-banding ............................................................................................................................ 30
1.3.2. On-chip SRAM memory ........................................................................................................ 30
1.3.3. On-chip Flash memory ......................................................................................................... 31
1.4. Boot configuration ............................................................................................................ 31
1.5. I/O compensation cell ...................................................................................................... 32
1.6. System configuration registers (SYSCFG) ................................................................... 33
1.6.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 33
1.6.2. EXTI sources selection register 0 (SYSCFG_EXTISS0) ...................................................... 34
1.6.3. EXTI sources selection register 1 (SYSCFG_EXTISS1) ...................................................... 35
1.6.4. EXTI sources selection register 2 (SYSCFG_EXTISS2) ...................................................... 36
1.6.5. EXTI sources selection register 3 (SYSCFG_EXTISS3) ...................................................... 38
1.6.6. System configuration register 2 (SYSCFG_CFG2) .............................................................. 39
1.6.7. I/O compensation control register (SYSCFG_CPSCTL) ...................................................... 40
1.7. Device electronic signature ............................................................................................ 41
1.7.1. Memory density information .................................................................................................. 41
1.7.2. Unique device ID (96 bits) .................................................................................................... 41
2. Flash memory controller (FMC) ............................................................................ 43
2.1. Overview ............................................................................................................................ 43
2.2. Characteristics .................................................................................................................. 43
2.3. Function overview ............................................................................................................ 43
2.3.1. Flash memory architecture ................................................................................................... 43
2.3.2. Read operations.................................................................................................................... 44
2.3.3. Unlock the FMC_CTL register .............................................................................................. 44
2.3.4. Page erase ............................................................................................................................ 44
2.3.5. Mass erase ........................................................................................................................... 45
2.3.6. Main flash programming ....................................................................................................... 47
2.3.7. Option byte erase.................................................................................................................. 48
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2.3.8. Option byte programming ..................................................................................................... 49
2.3.9. Option byte description ......................................................................................................... 50
2.3.10. Page erase/Program protection ............................................................................................ 51
2.3.11. Security protection ................................................................................................................ 51
2.4. Register definition ............................................................................................................ 53
2.4.1. Wait state register (FMC_WS) .............................................................................................. 53
2.4.2. Unlock key register (FMC_KEY) ........................................................................................... 53
2.4.3. Option byte unlock key register (FMC_OBKEY) ................................................................... 54
2.4.4. Status register (FMC_STAT) ................................................................................................. 54
2.4.5. Control register (FMC_CTL) ................................................................................................. 55
2.4.6. Address register (FMC_ADDR) ............................................................................................ 56
2.4.7. -Option byte status register (FMC_OBSTAT) ....................................................................... 57
2.4.8. Write protection register (FMC_WP) ..................................................................................... 57
2.4.9. Wait state enable register (FMC_WSEN) ............................................................................. 58
2.4.10. Product ID register (FMC_PID) ............................................................................................. 59
3. Power management unit (PMU) ............................................................................ 60
3.1. Overview ............................................................................................................................ 60
3.2. Characteristics .................................................................................................................. 60
3.3. Function overview ............................................................................................................ 60
3.3.1. Battery backup domain ......................................................................................................... 61
3.3.2. VDD/VDDA power domain .................................................................................................... 62
3.3.3. 1.2V power domain ............................................................................................................... 64
3.3.4. Power saving modes ............................................................................................................ 64
3.4. Register definition ............................................................................................................ 67
3.4.1. Control register (PMU_CTL) ................................................................................................. 67
3.4.2. Control and status register (PMU_CS) ................................................................................. 69
4. Reset and clock unit (RCU) ................................................................................... 72
4.1. Reset control unit (RCTL) ................................................................................................ 72
4.1.1. Overview ............................................................................................................................... 72
4.1.2. Function overview ................................................................................................................. 72
4.2. Clock control unit (CCTL) ................................................................................................ 73
4.2.1. Overview ............................................................................................................................... 73
4.2.2. Characteristics ...................................................................................................................... 75
4.2.3. Function overview ................................................................................................................. 75
4.3. Register definition ............................................................................................................ 79
4.3.1. Control register0 (RCU_CTL0) ............................................................................................. 79
4.3.2. Configuration register 0 (RCU_CFG0).................................................................................. 80
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 84
4.3.4. APB2 reset register (RCU_APB2RST) ................................................................................. 87
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4.3.5. APB1 reset register (RCU_APB1RST) ................................................................................. 88
4.3.6. AHB enable register (RCU_AHBEN) .................................................................................... 90
4.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 92
4.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 94
4.3.9. Backup domain control register (RCU_BDCTL) ................................................................... 96
4.3.10. Reset source /clock register (RCU_RSTSCK) ..................................................................... 97
4.3.11. AHB reset register (RCU_AHBRST) ..................................................................................... 99
4.3.12. Configuration register 1 (RCU_CFG1)................................................................................ 100
4.3.13. Configuration register 2 (RCU_CFG2)................................................................................ 101
4.3.14. Control register 1 (RCU_CTL1) .......................................................................................... 102
4.3.15. Additional clock control register (RCU_ADDCTL) .............................................................. 103
4.3.16. Additional clock interrupt register (RCU_ADDINT) ............................................................. 104
4.3.17. APB1 additional enable register (RCU_ADDAPB1EN) ...................................................... 105
4.3.18. APB1 additional reset register (RCU_ADDAPB1RST) ....................................................... 105
4.3.19. Voltage key register (RCU_VKEY) ..................................................................................... 106
4.3.20. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 106
5. Clock trim controller (CTC) ................................................................................. 108
5.1. Overview .......................................................................................................................... 108
5.2. Characteristics ................................................................................................................ 108
5.3. Function overview .......................................................................................................... 108
5.3.1. REF sync pulse generator .................................................................................................. 109
5.3.2. CTC trim counter ................................................................................................................. 109
5.3.3. Frequency evaluation and automatically trim process......................................................... 110
5.3.4. Software program guide ...................................................................................................... 111
5.4. Register definition .......................................................................................................... 112
5.4.1. Control register 0 (CTC_CTL0) ............................................................................................ 112
5.4.2. Control register 1 (CTC_CTL1) ............................................................................................ 113
5.4.3. Status register (CTC_STAT) ................................................................................................ 114
5.4.4. Interrupt clear register (CTC_INTC) .................................................................................... 116
6. Interrupt/event controller (EXTI) ......................................................................... 118
6.1. Overview .......................................................................................................................... 118
6.2. Characteristics ................................................................................................................ 118
6.3. Interrupts function overview ......................................................................................... 118
6.4. External interrupt and event (EXTI) block diagram ................................................... 121
6.5. External interrupt and Event function overview ........................................................ 121
6.6. Register definition .......................................................................................................... 123
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 123
6.6.2. Event enable register (EXTI_EVEN)................................................................................... 123
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6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 124
6.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 124
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 125
6.6.6. Pending register (EXTI_PD) ............................................................................................... 125
7. General-purpose and alternate-function I/Os (GPIO) ........................................ 127
7.1. Overview .......................................................................................................................... 127
7.2. Characteristics ................................................................................................................ 127
7.3. Function overview .......................................................................................................... 127
7.3.1. GPIO pin configuration ....................................................................................................... 129
7.3.2. Alternate functions (AF) ...................................................................................................... 129
7.3.3. Additional functions ............................................................................................................. 129
7.3.4. Input configuration .............................................................................................................. 129
7.3.5. Output configuration ........................................................................................................... 130
7.3.6. Analog configuration ........................................................................................................... 131
7.3.7. Alternate function (AF) configuration .................................................................................. 131
7.3.8. GPIO locking function ......................................................................................................... 132
7.3.9. GPIO single cycle toggle function ....................................................................................... 132
7.3.10. GPIO very high speed drive capability ............................................................................... 133
7.4. Register definition .......................................................................................................... 134
7.4.1. Port control register (GPIOx_CTL, x=A..D,F) ..................................................................... 134
7.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..................................................... 135
7.4.3. Port output speed register 0 (GPIOx_OSPD0, x=A..D,F) ................................................... 137
7.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F) ........................................................... 139
7.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ........................................................... 141
7.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 141
7.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F) ............................................................... 142
7.4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ..................................................... 142
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C) .................................... 143
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C) .................................... 144
7.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 145
7.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F) ................................................................... 146
7.4.13. Port output speed register 1 (GPIOx_OSPD1, x=A..D,F) ................................................... 146
8. CRC calculation unit (CRC) ................................................................................. 148
8.1. Overview .......................................................................................................................... 148
8.2. Characteristics ................................................................................................................ 148
8.3. Function overview .......................................................................................................... 149
8.4. Register definition .......................................................................................................... 151
8.4.1. Data register (CRC_DATA) ................................................................................................. 151
8.4.2. Free data register (CRC_FDATA) ....................................................................................... 151
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