verilog cpu

module controller(opcode,func,clk,reset,extop,alusrc,jump, regdst,regwr,memwr,memtoreg,npc_sel,aluctr); input [5:0]opcode,func; input clk,reset; output jump,extop,alusrc; output regdst,regwr; output memwr,memtoreg; output npc_sel; output [1:0]aluctr; wire[5:0] opcode,func; reg [1:0]aluctr; reg extop,regdst,jump,regwr,memwr,memtoreg,npc_sel,alusrc; always@(*)begin /*defaults*/ assign aluctr = 2'b00; assign regdst = 1'b1; assign regwr = 1'b1; assign memwr = 1'b0; assign memtoreg = 1'b0; assign npc_sel = 1'b0; assign alusrc = 1'b0; assign extop = 1'b0; assign jump = 1'b0; case(opcode) 6'b100011:begin /*lw*/ assign regdst = 1'b0; assign memtoreg = 1'b1; assign alusrc = 1'b1; assign extop = 1'b1; end 6'b101011:begin /*sw*/ assign alusrc = 1'b1; assign regwr = 1'b0; assign memwr = 1'b1; assign extop = 1'b1; end 6'b001101:begin /*ori*/ assign regdst = 1'b0; assign alusrc = 1'b1; assign extop = 1'b0; assign aluctr = 2'b10; end 6'b000100:begin /*beq*/ assign regwr = 1'b0; assign npc_sel =1'b1; assign aluctr = 2'b01; end 6'b000010:begin /*jump*/ assign regdst = 1'b0; assign regwr = 1'b0; assign jump = 1'b1; end 6'b001111:begin /*lui*/ assign aluctr = 2'b11; assign extop=1'b0; assign alusrc=1'b1; assign regdst=1'b0; end 6'b000000:begin /*addu or subu*/ assign aluctr=(func==6'b100011)?2'b01:2'b00; end endcase end endmodule