SystemVerilog for Verification(3rd)，好书，不需要过多解释，懂的自然懂。
Chris spear. Greg tumbush System Verilog for verification A Guide to learning the testbench Language Features Third edition pringer nris spear Greg Tumbush Synopsys, Inc University of Colorado, Colorado Springs Marlborough MA USa Colorado Springs Co. USA ISBN978-1-4614-0714-0 e-ISBN978-1-4614-0715-7 DOI10.1007/978-1-46140715-7 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011945681 O Springer Science+Business Media, LLC 2012 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher(Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights Printed on acid-free paper SpringerispartofSpringerScience+businessMedia(www.springer.com) This book is dedicated to my wife Laura, who takes care of everything, my daughter allie, long may you travel, my son Tyler, welcome back. and all the mice Chris sp This book is dedicated to my wife Carolye, who shrugged off my "I need to work on the book"requests with a patient smile, and to my toddler son Lucca who was always lable for play time Greg Tumbush Preface What is this book about? This book should be the first one you read to learn the System Verilog verification language constructs. It describes how the language works and includes many exam les on how to build a basic coverage-driven constrained-random. layered test bench using Object-Oriented Programming(OOP). The book has many guidelines on building testbenches, to help you understand how and why to use classes, randomization, and functional coverage. Once you have learned the language, pick up some of the methodology books listed in the References section for more infor mation on building a testbench Who should read this book? If you create testbenches, you need this book. If you have only written tests using Verilog or Vhdl and want to learn System verilog this book shows you how to move up to the new language features. Vera and specman users can learn how one language can be used for both design and verification. You may have tried to read the system verilog language Reference Manual but found it loaded with syntax but no guidelines on which construct to choose 2. Chris originally wrote this book because, like many of his customers, he spent much of his career using procedural languages such as C and verilog to write tests and had to relearn everything when OoP verification languages came along. He mad all the typical mistakes, and wrote this book so you won't have to repeat them Before reading this book, you should be comfortable with Verilog-1995. You do not need to know about Verilog-2001 or System Verilog design constructs, or System verilog assertions in order to understand the concepts in this book VIll Preface What is new in the third edition? This new edition of System Verilog for Verification has many improvements over the first two editions, written in 2006 and 2008, respectively Our universities need to train future engineers in the art of verification This edition is suitable for the academic environment, with exercise questions at the end of each chapter to test your understandin Qualifiedinstructorsshouldvisithttp://extras.springer.comforadditionalmate rials such as slides, tests, homework problems, solutions, and a sample syllabus suitable for a semester-long course The 2009 version of the IEEE 1800 System Verilog Language Reference Manual (LRM) has many changes, both large and small. This book tries to include the latest relevant information Accellera created UVM(Universal Verification Methodology) with ideas from VMM (Verification Methodology Manual), OVM (Open Verification Methodology), eRM(e reuse methodology), and other methodologies. Many of the examples in this book are based on VMM because its explicit calling of phases is easier to understand if you are new to verification. New examples are provided that show UVM concepts such as the test registry and configuration database When looking for a specific topic, engineers read books backwards, starting with the index so we boosted the number of entries Lastly, a big thanks to all the readers who spotted mistakes in the previous editions, from poor grammar to code that was obviously written on the morning after an 18-hour flight from Asia to Boston, or, even worse, changing a diaper This edition has been checked and reviewed many times over, but once again, all mistakes are ours Why was System Verilog Created? In the late 1990s, the Verilog Hardware Description Language(HDL) became the most widely used language for describing hardware for simulation and synthesis However, the first two versions standardized by the ieee(1364-1995 and 1364- 2001) had only simple constructs for creating tests. As design sizes outgrew the verification capabilities of the language, commercial Hardware verification Languages(HVLs)such as Open Vera and e were created. Companies that did not want to pay for these tools instead spent hundreds of man-years creating their own custom tools This productivity crisis, along with a similar one on the design side, led to the creation of Accellera, a consortium of EDa companies and users who wanted to create the next generation of Verilog. The donation of the Open Vera language formed the basis for the hvl features of System Verilog. Accellera's goal was met Preface in November 2005 with the adoption of the ieee standard 1800-2005 for System Verilog, IEEE(2005). In December 2009, the latest Verilog LRM, 1364 2005, was merged with the aforementioned 2005 System Verilog standard to create the ieee standard 1800-2009 for System Verilog Merging these two standards into a single one means there is now one language, System Verilog, for both design and verification Importance of a Unified Language Verification is generally viewed as a fundamentally different activity from design This split has led to the development of narrowly focused languages for verification and to the bifurcation of engineers into two largely independent disciplines. This specialization has created substantial bottlenecks in terms of communication between the two groups. System Verilog addresses this issue with its capabilities for both camps. Neither team has to give up any capabilities it needs to be successful, but the unification of both syntax and semantics of design and verification tools improves communication. For example, while a design engineer may not be able to write an object-oriented testbench environment, it is fairly straightforward to read such a test and understand what is happening, enabling both the design and verifica tion engineers to work together to identify and fix problems. Likewise, a designer understands the inner workings of his or her block, and is the best person to write assertions about it, but a verification engineer may have a broader view needed to create assertions between blocks Another advantage of including the design, testbench, and assertion constructs in a single language is that the testbench has easy access to all parts of the environment without requiring a specialized Application Programming Interface(API). The value of an hVl is its ability to create high-level, flexible tests, not its loop con- structs or declaration style. System Verilog is based on the verilog, VHDL, and C/C++ constructs that engineers have used for decades Importance of Methodology There is a difference between learning the syntax of a language and learning how to use a tool This book focuses on techniques for verification using constrained- random tests that use functional coverage to measure progress and direct the verifi cation. As the chapters unfold, language and methodology features are shown side by side. For more on methodology, see Bergeron et al.(2006) The most valuable benefit of System Verilog is that it allows the user to construct reliable, repeatable verification environments, in a consistent syntax, that can be used across multiple projects