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DSP原理及应用PPT教案.pptx
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2021-10-02
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DSP原理及应用PPT教案.pptx
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会计学 1
DSP 原理及应用
Dspsl
Digital Video
Wireless Infrastructure
Telecom Infrastructure
Wireless Infrastructure
Adaptive antenna array
Basestation
Media gateway
Telecom Infrastructure
Remote access server / universal
ports
PBX (private branch exchange)
VoIP gateway / server
Imaging
Imaging
Medical diagnostics
Machine vision / inspection
Radar, sonar and defense
Digital Video
Statistical remultiplexor/
broadband routers
Networked video surveillance
IP-based video conferencing
High-Performance
Digital Signal
Processing
Applications That
C6000™ DSP Serves
Well
第 1 页 / 共 62 页
Dspsl
Enhanced C64x+
™
Core:
Higher Performance
and Reduced Code
Size
Benet
Supporting
Architecture
Features
20% Higher
Cycle
Performance
Doubled
multiplication
bandwidth
Instruction set
enhancements for
FFT, FIR and DCT
New EDMA 3.0 engine
20–30%
Smaller
Code Size
16-bit compact
instructions
SPLOOP bu*er
Enhanced
Development
Real-time bandwidth
management
Memory protection
Better Debug
Exception handling
Cache coherency
visibility
Memory Protection
128
128
Unified Memory
Controller (UMC)
Memory
Protection
Bandwidth
Mgmt.
I
D
M
A
Data Path 1 Data Path 2
A Register File
Interrupt
& Exception
Controller
S1L1
M1
xx
xx
Data Memory Controller
(DMC)
External
Memory
Controller
(EMC)
DMA Slave
I/F
256
Program Memory
Controller (PMC)
256
128
Master Port
(CPU/ cache
req.)
Power
Control
256
L1D Cache/SRAM
L1P Cache/SRAM
L
2
C
a
c
h
e
/
S
R
A
M
To EDMA
3.0
256
D1
C64x+
CPU
M2
xx
xx
S2 L2D2
B Register File
Instruction Decode
16/32-bit Instruction Dispatch
SPLOOP Buffer
Instruction Fetch
Advanced Event
Triggering
(AET)
Memory Protection
Bandwidth Mgmt.
256
256
256
128
64
Bandwidth Mgmt.
32
TMS320C64x+™
DSP Core
New Feature
Improved From C64x
100% Object
Code Compatibility
第 2 页 / 共 62 页
Dspsl
16-bit FIR
24 taps,
128 samples
32-bit FIR
24 tap
64 samples
16-bit complex FIR
24 taps
40 samples
1.9x
1.5x
1.9x
Improved Filter Performance
Coefficients
1.6x
(3.9 us)
1.3x
(6.4 us)
1.6x
(7.7 us)
16-bit
Data
16-bit
32-bit
16-bit
32-bit
32-bit
Improved FFT Performance
C64x+
™
: 20% Cycle
Performance
Improvement
Due to New
Instruction Set
Architecture (ISA)
1.2x
1.3x
IDCT
DCT
Improved IDCT / DCT Performance
第 3 页 / 共 62 页
Dspsl
TMS320C6455 DSP Infrastructure
Aggregation: “Much Higher Bandwidth
and Lower System Cost”
Video Conferencing
PREVIOUSLY
RapidIO™
RapidIO
RapidIO
Decoding
Mixing &
Encoding
RapidIO
RapidIO
IP
Video Conferencing
NOW with C6455 DSP
IP
Decoding
Mixing &
Encoding
GEMAC
GEMAC
GEMAC
GEMAC
C6455
C6455
C6455
C6455
H.263
MPEG4
H.264
N*H.263
DSP1
M*MPEG4
DSP2
K*H.264
DSP3
Aggregator
(ASIC or
FPGA)
DSP4
第 4 页 / 共 62 页
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