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STM8S003K3 STM8S003F3 Contents 9 Electrical characteristics …46 9.1 Parameter conditions 46 9.1.1 Minimum and maximum values 46 9. 1.2 Typical values 46 9.1.3 Typical curves… 46 9. 1. 4 Loading capacitor 46 9.1.5 Pin input voltage 46 9.2 Absolute maximum ratings 47 9.3 Operating conditions 49 9.3.1 VCAP external capacitor 50 9.3.2 Supply current characteristics 9.3.3 External clock sources and timing characteristics 60 9.3. 4 Internal clock sources and timing characteristics 62 9.3.5 Memory characteristics 64 9. 3. l/O port pin characteristics 9.3.7 Reset pin characte 74 9.3.8 SPI serial peripheral interface ....... 9.3.9C interface characteristics 9.3. 10-bit ADC characteristics 81 9.3.11 EMC characteristics 85 10 Package information ∴89 10.1 32-pin LQFP package mechanical data 89 10.2 20-pin TSSOP package mechanical data 90 10.3 20-lead UFQFPN package mechanical data 92 11 Thermal characteristics 94 11. 1 Reference document 94 11.2 Selecting the product temperature range 94 12 Ordering information 96 13STM8 development tools…,…,,97 13.1 Emulation and in-circuit debugging tools 13.2 Software tools 13.2.1 STM8 toolset 98 13.2.2C and assembly toolchains 98 13.3 Programming tools 98 14 Revision history,… 99 DocID018576 Rev 3 3/100 List of tables STM8S003K3 STM8S003F3 List of tables Table 1. stm8s003xx value line features Table 2. Peripheral clock gating bit assignments in CLK_ PCKENR1/2 registers 13 Table 3. tiM timer features 15 Table 4. Legend/abbreviations for pinout tables 18 Table 5. LQFP32 pin description 19 Table 6. STM8S003F3 pin description 22 Table 7. IO port hardware register map 26 Table 8. General hardware register map .27 Table 9. CPU/SWIM/debug module/interrupt controller registers Table 10 Interrupt mapping 39 Table 11. option bytes 99 Table 12 Option byte description Table 13. STM8S003K3 alternate function remapping bits for 32-pin devices 43 Table 14. STM8S003F3 alternate function remapping bits for 20-pin devices 44 Table 15. Voltage characteristics Table 16. Current characteristics 1,a Table 17. Thermal characteristics 48 Table 18. General operating conditions 49 Table 19. Operating conditions at power-up/power-down Table 20 Total current consumption with code execution in run mode at VDp=5. 50 Table 21. Total current consumption with code execution in run mode at Von =3.3v 52 Table 22. Total current consumption in wait mode at VDD=5V 53 Table 23 Total current consumption in wait mode at Table 24. Total current consumption in active halt mode at VDp=5 V 54 Table 25. Total current consumption in active halt mode at Vdp=3.3V 54 Table 26 Total current consumption in halt mode at VDD=5V 55 Table 27. Total current consumption in halt mode at Voo =3.3 v Table 28 Wakeup times Table 29. Total current consumption and timing in forced reset state 56 .57 Table 30. Peripheral current consumption Table 31 hse user external clock characteristics 60 Table 32 hse oscillator characteristics Table 33. hsl oscillator characteristics 62 Table 34. LsI oscillator characteristics Table 35. RAM and hardware registers ∴64 Table 36. Flash program memory and data EEPROM 65 Table 37 o static characteristics 66 Table 38. Output driving current (standard ports) 68 Table 39. Output driving current(true open drain ports 68 Table 40 Output driving current(high sink ports) 69 Table 41. NRST pin characteristics 74 Table 42 sPi characteristics 78 Table 43.2C characteristics 80 Table 44. Adc characteristics 82 Table 45. ADC accuracy with Rain <10 kQ, VDD =5V .82 Table 46. ADC accuracy with RAIN 10 kQ RAIN, VDD=3.3V Table 47. ems data 86 4/100 DocID018576 Rev 3 STM8S003K3 STM8S003F3 List of tables Table48. EMi data∴ aa:.aa..aa.:.::::::aa.aa. 86 Table 49. Esd absolute maximum ratings Table 50. Electrical sensitivities 88 Table 51 32-pin low profile quad flat package mechanical data 89 Table 52 20-pin, 4. 40 mm body, 0. 65 mm pitch mechanical data Table 53. 20-lead ultra thin fine pitch quad flat no-lead package(33)mechanical data 2 Table 54. Thermal characteristics 94 Table 55. Document revision history 99 DocID018576 Rev 3 5/100 List of figures STM8S003K3 STM8S003F3 List of fiqures igure 1 Block diagram Figure2. Flash memory organization…… .12 Figure 3. STM8S003K3 LQFP32 pinout 18 Figure 4. STM8S003F3 TSSOP20 pinout 21 Figure 5. STM8S003F3 UFQFPN20-pin pinout 22 Figure 6. Memory map 25 Figure7. Pin loading conditions……… 46 Figure 8 Pin input voltage 47 Figure: Comar Versus\DD…… .50 Figure 10. External capacitor CEXT 50 Figure 11. Typ IDD(RUN)VS VDD HSE user external clock, fcPU=16 MHZ 58 Figure 12. Typ DD(RUN)VS fcPU HSE user external clock, VDD=5 V 58 Figure 13 Typ IDD(RUN) VS VDD HSI RC OSC, fcPU=16 MHz 59 Figure 14. Typ IDD(wF) VS VDD HSE user external clock, fcPu =16 MHz 59 Figure 15. Typ IDD(WFI)VS fcpu HSE user external clock, DD=5V 60 Figure 16. Typ IDD() VS. VDD HSI RC OSC, cPU=16 MHZ 60 Figure 17 HSE external clock source Figure 18 HSE oscillator circuit diagram 62 igure 19. Typical HSI frequency variation vs Vpp 4 temperatures 63 Figure 20. Typical LSI frequency variation vs VDp 4 temperatures 64 Figure 21. Typical VI and vIh vs Vop 4 temperatures Figure 22. Typical pull-up resistance Vs VDp@ 4 temperatures .67 Figure23. Typical pu‖ up current Vs VDD@4 temperatures…… 68 Figure 24. Typ. VOL O VDD= 5 V(standard ports) 70 Figure 25. Typ. Vo Vop =3.3 V(standard ports) 70 Figure 26. Typ. VoL Vdp =5V(true open drain ports .71 Figure 27 Typ. VOL VDD =3.3V(true open drain ports) Figure28.Typ.VoL@VD=5∨( high sink ports)… 72 Figure 29 Typ. VOL VDD =3.3 V(high sink ports) 72 Figure 30. Typ. VDD - VOHO VDD =5V(standard ports 73 igure 31. Typ. VDD-VOH O VDD =3.3V(standard ports) 73 Figure 32. Typ. VDD -VOH@ VDp =5V(high sink ports 74 Figure 33. Typ. VDD-VOHQ VDD =3.3V(high sink ports Figure 34. Typical NRST VI and ViH VS VDD Q 4 temperatures ∴74 76 Figure 35. Typical NRST pull-up resistance vs VDD 4 temperatures 76 Figure 36. Typical NRST pull-up current vs Vpp 4 temperatures 77 Figure 37. Recommended reset pin protection Figure 38. SPI timing diagram -slave mode and CPHA=0 79 Figure 39. SPI timing diagram - slave mode and CPha=1 79 Figure 40. SPI timing diagram-master mode 80 Figure 41. Typical application with C bus and timing diagram ... 84 Figure 42. ADC accuracy characteristics 84 Figure 43. Typical application with ADC 85 Figure 44 32-pin low profile quad flat package(7X 7) 89 Figure 45. 20-pin, 4.40 mm body, 0.65 mm pitch 90 Figure 46 20-lead ultra thin fine pitch quad flat no-lead package outline(3x3) 92 Figure 47. STM8S003x value line ordering information scheme 96 6/100 DocID018576 Rev 3 STM8S003K3 STM8S003F3 Introduction Introduction This datasheet contains the description of the device features, pinout, electrical characteristics mechanical data and ordering information e For complete information on the sTM8s microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual(RM0016) o For intormation on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051) For information on the debug and SWiM(single wire interface module)refer to the STM8 SWIM communication protocol and debug module user manual (UM0470) For information on the STM8 core, please refer to the STM8 CPU programming manual (PMO044) DocID018576 Rev 3 7/100 Description STM8S003K3 STM8S003F3 2 Description The STM8S003x value line 8-bit microcontrollers feature 8 Kbytes Flash program memory plus integrated true data eeprom. the stm8s microcontroller family reference manual (RMo016)refers to devices in this family as low-density. They provide the following benefits performance, robustness, and reduced system cost Device performance and robustness are ensured by integrated true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system The system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset Full documentation is offered as well as a wide choice of development tools Table 1: stm8s003xx value line features Device STM8S003K3 STM8S003F3 Pin count 32 20 Maximum number of GPIOs(1/Os) 28 16 Ext interrupt pins 27 16 Timer CaPCom channels Timer complementary outputs 734 725 A/D converter channels High sink I/Os 21 12 Low density Flash program memory (bytes) 8K 8K RAM(bytes 1K 1K True data EEPROM(bytes) 128 128 Multipurpose timer(TIM1), SPl, I"C, UART Peripheral set window WDG, independent WDG, ADC, PWM timer(TIM2),8-bit timer(TIM4) Without read-while-write capability 8/100 DocID018576 Rev 3 STM8S003K3 STM8S003F3 Block diagram 3 Block diagram Figure 1: Block diagram DocID018576 Rev 3 9/100 Product overview STM8S003K3 STM8S003F3 Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals For more detailed information please refer to the corresponding family reference manual (RMo016) Central processing unit sTM8 The 8-bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers o Harvard architecture 3-stage pipeline a 32-bit wide program memory bus-single cycle fetching for most instructions X and Y 16-bit index registers-enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter- 16-Mbyte linear memory space e 16-bit stack pointer-access to a 64 K-level stack 8-bit condition code register-7 condition flags for the result of the last instruction Addressing o 20 addressing modes o Indexed indirect addressing mode for look-up tables located anywhere in the address space o Stack pointer relative addressing mode for local variables and parameter passing Instruction set o 80 instructions with 2-byte average instruction size e Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulatio Data transfer between stack and accumulator(push/pop )with direct stack access o Data transfer using the X and Y registers or direct memory-to-memory transfers 4.2 Single wire interface module(swIM)and debug module(DM) The single wire interface module and debug module permits non- intrusive real-time in-circuit debugging and fast memory programming 10/100 DocID018576 Rev 3

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