stm31f405和stm32f407系列资源-CSDN文库

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This is information on a product in full production.

September 2016 DocID022152 Rev 8 1/202

STM32F405xx

STM32F407xx

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB

OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

Datasheet - production data

Features

• Core: ARM

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 168 MHz,

memory protection unit, 210 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

• Memories

• Up to 1 Mbyte of Flash memory

• Up to 192+4 Kbytes of SRAM including 64-

Kbyte of CCM (core coupled memory) data

RAM

• Flexible static memory controller supporting

Compact Flash, SRAM, PSRAM, NOR and

NAND memories

• LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 1.8 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1%

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low-power operation

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 20×32 bit backup

registers + optional 4 KB backup SRAM

• 3×12-bit, 2.4 MSPS A/D converters: up to 24

channels and 7.2 MSPS in triple interleaved

mode

• 2×12-bit D/A converters

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

• Up to 17 timers: up to twelve 16-bit and two 32-

bit timers up to 168 MHz, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

• Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

– Cortex-M4 Embedded Trace Macrocell™

• Up to 140 I/O ports with interrupt capability

– Up to 136 fast I/Os up to 84 MHz

– Up to 138 5 V-tolerant I/Os

• Up to 15 communication interfaces

– Up to 3 × I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO

7816 interface, LIN, IrDA, modem control)

– Up to 3 SPIs (42 Mbits/s), 2 with muxed

full-duplex I

S to achieve audio class

accuracy via internal audio PLL or external

clock

– 2 × CAN interfaces (2.0B Active)

– SDIO interface

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

UFBGA176

(10 × 10 mm)

LQFP176 (24 × 24 mm)

WLCSP90

(4.223x3.969 mm)

&"'!

www.st.com

DocID022152 Rev 8 3/202

STM32F405xx, STM32F407xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.1 ARM

Cortex

-M4 core with FPU and embedded Flash and SRAM . . 20

2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 20

2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 21

2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 23

2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 29

2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 29

2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2.20 V

BAT

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 34

2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 36

2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 36

2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Contents STM32F405xx, STM32F407xx

4/202 DocID022152 Rev 8

2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 37

2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 38

2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 82

5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 82

5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 83

5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 106

DocID022152 Rev 8 5/202

STM32F405xx, STM32F407xx Contents

5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 112

5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.3.20 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . 133

5.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.3.23 V

BAT

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.3.26 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 161

5.3.28 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 162

5.3.29 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.1 WLCSP90 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

6.3 LQPF100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

6.4 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

6.5 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6.6 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

6.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 186

A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 188

A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

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