ARM Architecture Reference Manual ARMv8, f - ARM Limited.pdf

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资源仅供学习交流使用,可以官方免费下载,个人上传仅供国内需要的人搬运,链接见下面声明: ARMv8 架构手册 Part A ARMv8 Architecture Introduction and Overview Chapter A1 Introduction to the ARMv8 Architecture A1.1 About the ARM architecture ................................................................................. A1-30 A1.2 Architecture profiles ............................................................................................. A1-32 A1.3 ARMv8 architectural concepts ............................................................................. A1-33 A1.4 Supported data types ........................................................................................... A1-36 A1.5 Floating-point and Advanced SIMD support ........................................................ A1-46 A1.6 Cryptographic Extension ...................................................................................... A1-52 A1.7 The ARM memory model ..................................................................................... A1-53 Part B The AArch64 Application Level Architecture Chapter B1 The AArch64 Application Level Programmers’ Model B1.1 About the Application level programmers’ model ................................................. B1-58 B1.2 Registers in AArch64 Execution state .................................................................. B1-59 B1.3 Software control features and EL0 ....................................................................... B1-64
In this document, where the term ARM is used to refer to the company it means"ARM or any of its subsidiaries as appropriate The terIn ARM can refer to versions of the ARM architecture, for example ARMv? refers to version 7 ofthe ARM architecture. The context makes it clear when the term is used in this way This document dcscribcs only thc ARMvg-A architecture profile For thc behaviors rcquircd by the armv7-a and ARMv7-R architecture profiles, see the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition Web address http://www.arm.com ARM DDI 0487A b Copyright O 2013 ARM Limited. All rights reserved 1D122413 Non -Confidentia/ Beta Copyright O 2013 ARM Limited. All rights reserved ARM DDI 0487A b Non -Confidentia/ Beta 1D122413 Contents ARM Architecture reference manual rmy8 for ARMV8-A architecture profile Preface About this manual Using this manual Conventions Additional reading… Feedback PartA ARMv8 Architecture Introduction and overview Chapter A1 Introduction to the army Architecture Al.1 About the arm architecture A130 A1.2 Architecture profiles A1-32 A1.3 ARMv8 architectural concepts A1.4 Supported data types A136 A1.5 Floating-point and Advanced SIMD support A1-46 A1.6 Cryptographic Extension A152 he ARM memory model A1-53 Part B The AArch64 Application Level Architecture Chapter B1 The AArch64 Application Level Programmers'Model About the Application level programmers model B1-58 B1.2 Registers in AArch64 Execution state B159 B1.3 Software control features and elo B1-64 ARM DDI 0487A b Copyright 2013 ARM Limited. All rights reserved |D122413 Non-Confidential- Beta Chapter B2 The AArch64 Application Level Memory Model B2.1 Address space B2-68 B2.2 Memory type overview ∴B2-69 B2.3 Caches and memory hierarchy B2-70 B2.4 Alignment support B2-75 B2.5 Endian support B2-76 B2.6 Atomicity in the aRM architecture B2-79 B2.7 Memory orderin B2.8 Memory types and attributes .B2-89 B2. 9 Mismatched memory attributes ......... .B297 B2. 10 Synchronization and semaphores B299 Part c The AArch64 Instruction Set Chapter C1 The A64 Instruction Set C11 Introduction C1-110 C1.2 Structure of the A64 assembler language C1-111 C1. 3 Address generation C1-116 C1. 4 Instruction aliases C1-119 Chapter c2 About the A64 Instruction Descriptions C2. 1 Format of the A64 instruction descriptions ∴C2-122 Chapter c3 A64 Instruction Set Overview C3. 1 Branches, Exception generating, and System instructions C3-126 C3.2 Loads and stores 3-131 C3. 3 Data processing-immediate C3-142 C3.4 Data processing-register ∴C3-147 C3.5 Data processing-SIMD and floating-point C3-154 Chapter C4 A64 Instruction Set Encoding C4.1 A64 instruction index by encoding c4-174 C4.2 Branches, exception generating and system instructions C4-175 C4.3 Loads and stores C4.178 C4. 4 Data processing-immediate C4-195 C4.5 Data processing-register C4-198 C4.6 Data processing- SIMD and floating point C4-205 Chapter c5 The A64 System Instruction Class C5. 1 About the System instruction and System register descriptions C5-232 C5.2 The System instruction class encoding space C53 PSTATE and special purpose registers.........…………c5252 C54 A64 system instructions for cache maintenance c5-303 C55 A64 system instructions for address translation 5-319 C5.6 A64 system instructions for TLB maintenance.. c5-332 Chapter C6 A64 Base Instruction Descriptions C6.1 Introduction C6-382 C62 Register size c6383 C6.3 Use of the pc c6-384 C6. 4 Use of the stack pointer C6.5 Condition flags and related instructions .C6-386 C6.6 Alphabetical list of instructions C6387 Chapter c7 A64 Advanced SIMD and Floating- point Instruction Descriptions C7.1 About the A64 Advanced SIMD and floating-point instruction descriptions C7-770 Copyright 2013 ARM Limited. All rights reserved ARM DDI 0487A b Non-Confidentia/-Beta C7. 2 About the SIMD and floating-point instructions C777 C7. 3 Alphabetical list of floating-point and Advanced simd ins C7773 Part D The AArch64 System Level Architecture Chapter D1 The AArch64 System Level Programmers'Model D1.1 Exception levels D1.2 Exception terminolo D1-1401 D1.3 Execution state D11403 D1. 4 Security state .aaa“.::: D1-1404 D1.5 Virtualization D1-1406 D1.6 Registers for instruction processing and exception handling .D1-1408 D1.7 Process state. PStatE .D1-1413 D1.8 Program counter and stack pointer alignment D1-1415 D1.9 Reset D1-1417 D1.10 EXception entry .D1-142 D1. 11 EXception return .D1-1437 D1. 12 The Exception level hierarchy D1-1440 D1.13 Synchronous exception types, routing and priorities D1-1447 D1.14 Asynchronous exception Iting, masking and priorities D1-1453 D1.15 Controls at higher Exception levels D1-1459 D1. 16 System calls .D1-1501 D1. 17 Mechanisms for entering a low-power state D1-1503 D1.18 Self-hosted debug D1-1509 Dl.19 The performance monitors extension D1-1511 D1.20 Interprocess D1-1512 D1.21 Supported configurations D1-1524 Chapter D2 AArch64 Self-hosted Debug D2. 1 About debug exceptions .D2-1530 D2.2 The debug exception enable controls ..D2-1533 D2.3 Routing debug exceptions D2-1534 D2. 4 Enabling debug exceptions from the current Exception level and Security state D2-1536 D2.5 The effect of powerdown on debug exceptions D2-1539 D2.6 Summary of the permitted routing and enabling of debug exceptions D2-1540 D2.7 Pseudocode descriptions of debug exceptions D2-1542 D2.8 Software Breakpoint Instruction exceptions D2-1544 D2.9 Breakpoint exceptions D2-1546 D2. 10 Watchpoint exceptions D2-1564 D2.11 Vector Catch exceptions D2-1578 D2.12 Software Step exceptions D2-1579 D2.13 Synchronization and debug exceptions D2-1593 Chapter D3 The Aarch 64 System Level Memory Model D3. 1 About the memory system architecture D3-1596 D3.2 Address space D3-159 D3. 3 Mixed-endian support D3-1598 D3.4 Cache support D3-1599 D3.5 External abort D3-1619 D3.6 Memory barrier instructions D3-1621 D3.7 Pseudocode details of general memory system instructions D3-1622 Chapter D4 The AArch64 Virtual Memory System Architecture D4.1 About the virtual Memory System Architecture(MsA)……..… ..D4-1634 D4.2 The VMsAv8-64 address translation system D4.1636 D4.3 Translation table walk examples D4-1686 ARM DDI 0487Ab Copyright 2013 ARM Limited. All rights reserved D122413 Non -Confidentia/-Beta D4.4 VMSAv8-64 translation table format descriptors D4-1698 D4.5 Access controls and memory region attributes ““..·...:a D4-1707 D4.6 MMU faults D4.1722 D4.7 Translation Lookaside Buffers(TLBs) D4-1730 D4.8 Caches in a VMSa implementation D4-1744 Chapter D5 The Performance Monitors Extension D5.1 About the performance monitors D5-1748 D52 Accuracy of the Performance Monitors D5-1750 D53 Behavior on overflow D5-1752 D5. 4 Attributability............ D5-1754 D5.5 Effect of el3 and el2 D5-1755 D5.6 Event filtering D5-1757 D57 Performance Monitors and Debug state D5-1758 D5 8 Counter enables ∴D5-1759 D5.9 Counter access D5-1760 D5. 10 Event numbers and mnemonics .D5-1762 D5.11 Performance monitors Extension registers D5-1777 D5.12 Pseudocode details D5-1780 Chapter D6 The generic Timer D6. 1 About the generic timer D6-1784 D6.2 About the generic Timer registers .D6-1791 Chapter D7 AArch64 System Register Descriptions D7.1 About the AArch64 System registers D7-1794 D72 General system control registers…… ∴D7-1798 D7. 3 Debug registers D7-1989 D7. 4 Performance monitors registers ,,, D7-2046 D7.5 Generic Timer registers D7-208 D7.6 Generic Interrupt Controller CPU interface registers D7-2106 Part e The AArch32 Application Level Architecture Chapter E1 The AArch32 Application Level Programmers'Model E1 1 About the application level programmers' model E1-2202 E12 Additional information about the programmers' model in AArch32 state E1-2203 E1.3 Advanced SIMD and floating-point instructions E1-2216 E1.4 Coprocessor support E1-2244 E1.5 Exceptions E1-2245 Chapter E2 The AArch32 Application Level Memory Model Address space 2-2248 E2.2 Memory type overview E2-2250 E2.3 Caches and memory hierarchy E2-2251 lignment supp E2.5 Endian support E2-2258 E2.6 Atomicity in the ARM architecture .E2-2261 E2.7 Memory ordering… E22266 E2.8 Memory types and attributes ....... E2-2273 E2.9 Mismatched memory attributes E2-2281 E2.10 Synchronization and semaphores E2-2284 Copyright 2013 ARM Limited. All rights reserved ARM DDI 0487A b Non-Confidentia/-Beta Part F The aarch 32 Instruction sets Chapter F1 The aarch 32 Instruction sets overview F1.1 Support for instructions in difterent versions of the ARM architecture F1-2296 F1.2 Unified Assembler Language F1-2297 F1.3 Branch instructions F12299 F1.4 Data- processing instructions F12300 F1.5 Status register access instructions F1-2308 F1.6 Load/store instructions F1-2309 F1. 7 Load/store multiple instructions F12311 F18 Miscellaneous instructions F1-2312 F1.9 Exception-generating and exception-handling instructions F1-2313 F1.10 Coprocessor instructions F1-2314 F1.11 Advanced SIMD and floating-point load/store instructions F1-2315 F1. 12 Advanced SIMd and floating-point register transfer instructions .F1-2317 F1. 13 Advanced siMD data-processing instructions F1-2318 F1. 14 Floating-point data-processing instructions .F12324 Chapter F2 About the T32 and A32 Instruction Descriptions F2.1 Format of instruction descriptions F22326 F22 Standard assembler syntax fields…… F22330 F2.3 Conditional execution F2-2331 F2. 4 Shifts applied to a registe F22334 F2.5 Memory accesses F2-2337 F2.6 Integer arithmetic in the t 32 and A32 instruction sets F2-2338 F2.7 Encoding of lists of general-purpose registers and the pc F2-2341 F2.8 Additional pseudocode support for instruction descriptions........... F2-2342 Chapter F3 T32 Base Instruction Set Encoding F3.1 T32 instruction set encoding F3-2346 F3.2 16-bit T32 instruction encoding F32349 F3.3 32-bit T32 instruction encoding aaaaaa F3-2356 Chapter F4 A32 Base Instruction Set Encoding -4.1 A32 instruction set encoding F4-2380 F4.2 Data-processing and miscellaneous instructions F42383 F4.3 Load/ store word and unsigned byte F4-2395 F4,4 Media instructions F42396 F4.5 Branch branch with link and block data transfer F4-2401 F4.6 Coprocessor instructions, and St F4.7 Unconditional instructions F4-2403 Chapter F5 T32 and A32 Instruction Sets Advanced SIMD and floating-point Encodings F5.1。 verview∴ F5-2408 F52 Advanced SIMD and floating-point instruction syntax F5-2409 F5 3 Regi F5-2413 F5. 4 Advanced SiMD data-processing instructions F5-2415 F5. 5 Floating-point data-processing instructions F5-2427 F5.6 Advanced SIMD and floating-point register load/store instructions F5-2430 F5.7 Advanced siMd element or structure load/store instructions .F5-2431 F5.8 8, 16, and 32-bit transfers accessing the sIMD and floating- point register file F5-2434 F5.9 64-bit transfers accessing the SIMD and floating-point register file F5-2435 Chapter F6 ARMv8 Changes to the t32 and A32 Instruction Sets F6.1 The a32 and t32 instruction sets F6-2438 F6.2 Partial deprecation of IT ARM DDI 0487Ab Copyright 2013 ARM Limited. All rights reserved D122413 Non -Confidentia/-Beta F6.3 New A32 and T32 Load-Acquire/Store- Release instructions F6-2440 F6. 4 New A32 and T32 scalar floating-point instructions F6-2441 F6.5 New A32 and T32 Advanced SIMD floating-point instructions F6-244 F6.6 New A32 and T32 instructions provided by the Cryptographic EXtension F6-2446 6.7 New A32 and t32 System instructions F6-2447 Chapter F7 T32 and A32 Base Instruction Set Instruction Descriptions 7.1 Alphabetical list of T32 and A32 base instruction set instructions F7-2450 F72 General restrictions on system instructions F7-2993 F7.3 Encoding and use of Banked register transfer instructions .F7-2994 F7.4 Alphabetical list of system instructions ∴F7-2998 Chapter F8 T32 and A32 Advanced SIMD and floating-point Instruction Descriptions F8. 1 Alphabetical list of floating-point and Advanced SIMD instructions F8-3036 F8.2 Advanced SIMD and floating-point system instructions .. F8-3358 Part G The AArch32 System Level Architecture Chapter G1 The AArch32 System Level programmers' Mode G1.1 About the AArch32 System level programmers' model G13366 G1.2 Exception levels G13367 Exception terminology G1-3368 G1 4 Execution state G1-3370 G15 nstruction Set state .G13372 G1.6 Security state G1-3373 G1.7 irtualization G1-3376 G1.8 AArch 32 PE modes, general-purpose registers, and the PC G13378 G19 Instruction set states G1-3394 G1. 10 Handling exceptions that are taken to an Exception level using AArch 32 G1-3396 G1. 11 Asynchronous exception behavior for exceptions taken from AArch32 state. G1- 3418 G1.12 AArch32 state exception descriptions G1-3428 G1.13 Reset into aarch 32 state G13454 G1.14 Mechanisms for entering a low-power state G1-3457 G1.15 The conceptual coprocessor interface and system control G13463 G1.16 Advanced SIMD and floating- point support G13466 G1.17 Configurable instruction enables, disables, and traps G1-3475 Chapter G2 AArch32 Self-hosted Debug G2.1 About debug exceptions G2-3510 G2.2 The debug exception enable controls G2-3513 G2.3 Routing debug exceptions G2-3514 G2. 4 Enabling debug exceptions from the current Exception level and Security state G2-3516 G2.5 The effect of powerdown on debug exceptions G2-3519 G2.6 Summary of permitted routing and enabling of debug exceptions G2-3520 G2.7 Pseudocode descriptions of debug exceptions G2-3522 G2.8 Software breakpoint Instruction exceptions G23523 G2. 9 Breakpoint exceptions G2-3526 G2. 10 Watchpoint exceptions G2-3550 G2.11 Vector Catch exceptions G2-3564 G2.12 Synchronization and debug exceptions G2-3572 Chapter G3 The AArch32 System Level Memory Model G3.1 About the memory system architecture G3-3576 G3.2 Address spa G33577 G3.3 Mixed-endian support G3-3578 G3.4 Cache support G3-3580 Copyright 2013 ARM Limited. All rights reserved ARM DDI 0487A b Non-Confidentia/-Beta

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