STM32F103ZE数据手册(官方英文原版)

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STM32F103ZE数据手册(官方英文原版)
STM32F103xC. STM32F103XD. STM32F103xE Contents 2.3.29 Serial wire JTAG debug port (SWJ-DP) .23 2.3.30 Embedded trace macrocell Pinouts and pin descriptions.∴…∴ 24 345 Memory mapping 38 Electrical characteristics 39 5.1 Parameter conditions n■ 5.1.1 Minimum and maximum values 5.1.2 Typical val 5.1.3 Typical curves 39 5.1. 4 Loading capacit 39 5.1.5 Pin input voltage 39 6 Power supply scheme 40 5.1.7 Current consumption measurement 5.2 Absolute maximum ratings 41 5.3 Operating conditions 42 5.3.1 General operating conditions 42 5.3.2 Operating conditions at power-up / power-down ,,43 5.3. 3 Embedded reset and power control block characteristics 5.3. 4 Embedded reference voltage 44 5.3.5 Supply current characteristics 44 5.3.6 External clock source characteristics 55 5.3.7 Internal clock source characteristics 60 5.3. 8 PLL characteristics 62 5.3. 9 Memory characteristics 5.3.10 FSMc characteristics 5.3.11 EMC characteristics 5.3.12 Absolute maximum ratings (electrical sensitivity) 84 5.3.13 1 o current injection characteristics 85 5.3.14 10 port characteristIcs 86 5.3.15 NRST pin characteristics 91 5.3.16 TIM timer characteristics 92 5.3.17 Communications interfaces ■面 ,93 5.3.18 CAN (controller area network)interface .....102 5.3.19 12-bit ADC characteristics 103 Doc ID 1461 1 Rev 8 3/130 Contents STM32F103XC, STM32F103xD. STM32F103XE 5.3.20 DAC electrical specifications 108 5.3.21 Temperature sensor characteristics 110 Package characteristics∴.∴….∴…∴. 111 6.1 Package mechanical data 6.2 Thermal characteristics 120 6.2.1 Reference document 120 6.2.2 Selecting the product temperature range 121 Part numbering n123 Revision history ,,,,,,,,,,,,,,,,,∴,.,124 4/130 Doc ID 1461 1 Rev 8 STM32F103xC, STM32F103XD. STM32F103XE List of tables List of tables Table 1 Device summary...... Table 2. STM32F103X C, STM32F103XD and STM32F103XE features and peripheral counts..1 Table 3. STM32F103XX family ,,,,,14 Table 4. High-density timer feature comparison 19 Table 5. High-density STM32F103xx pin definitions Table 6. FSMC pin definition 36 Table 7. Voltage characteristics ,,,,,41 Table 8. Current characteristics Table 9. Thermal characteristics 42 Table 10. General operating conditions 42 Table 11. Operating conditions at power-up/ power-down .43 Table 12. embedded reset and power control block characteristics Table 13. Embedded internal reference voltage 44 Table 14. Maximum current consumption in Run mode, code with data processing running from flash 45 Table 15. Maximum current consumption in Run mode, code with data processing running from ram Table 16 Maximum current consumption in Sleep mode, code running from Flash or RAM,"..45 Table 17. Typical and maximum current consumptions in Stop and standby modes 48 Table 18. Typical current consumption in Run mode, code with data processing running from Flash ..... 52 Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM : 53 Table 20. Peripheral current consumption ..54 Table 21. High-speed external user clock characteristics 55 Table 22. Low-speed external user clock characteristics 56 Table 23. HSE 4-16 MHz oscillator characteristics 58 Table 24. LSE oscillator characteristics (fLSE =32.768 kHz) 59 Table 25. Hsi oscillator characteristics ...60 Table 26, lsl oscillator characteristics 60 T able 27. Low-power mode wakeup timings Table 28. PLL characteristics 62 Table 29. Flash memory characteristics 62 Table 30. Flash memory endurance and data retention .,,63 Table 31. Asynchronous non-multiplexed SrAM/PSRAM/NOR read timings .,64 Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings 65 Table 33. Asynchronous multiplexed PSRAM/NOR read timings 66 Table 34. Asynchronous multiplexed PSRAM/NOR write timings ...68 Table 35. Synchronous multiplexed NOR/PSRAM read timings 70 Table 36. Synchronous multiplexed PSRAM write timings Table 37. Synchronous non-multiplexed Nor/PSRAM read timings 73 Table 38. Synchronous non-multiplexed PSRAM write timings 74 Table 39. Switching characteristics for PC Card/CF read and write cycles ,79 Table 40. Switching characteristics for NAND Flash read and write cycles 82 Table 41. EMs characteristics ......83 Table 42. emi characteristics 84 Table 43. ESd absolute maximum ratings ...,..84 Table 44. Electrical sensitivities ,85 Doc ID 1461 1 Rev 8 5/130 List of tables STM32 F103XC. STM32F103xD, STM32F103XE Table 45. 10 current injection susceptibility ..85 Table 46. I/o static characteristics 86 Table 47. Output voltage characteristics 89 Table 48. IO AC characteristics 90 Table 49. NRST pin characteristics Table 50. TIMx characteristics 92 Table 51. 12C characterist 93 Table 52. SCL frequency(pCLK1=36 MHZ. VDD=3.3 V) 94 Table 53. SPI characteristics 95 Table 54. 2s characteristics 98 Table 55. SD/MMC characteristics 101 Table 56. USB startup time. .,.,,101 Table 57. USB dc electrical characteristics 102 Table 58. USB: full-speed electrical characteristics 102 Table 59. Adc characteristics ..103 Table 60. RAIN max for fADC=14 MHz ,,104 Table 61. ADC accuracy -limited test conditions 104 Table 62 ADC accuracy 105 Table 63. Dac characteristics ..,108 Table 64, ts characteristics Table 65. Recommended PCB design rules(0.80/0.75 mm pitch BGA) 112 Table 66. LFBGA144-144-ball low profile fine pitch ball grid array, 10 X 10 mm 0. 8 mm pitch, package data 113 Table 67. LFBGA100-10 x 10 mm low profile fine pitch ball grid array package mechanical data ,,,,,,114 Table 68. WLCSP, 64-ball 4.466x 4 395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data ,,115 Table 69. Recommended PCB design rules(0. 5mm pitch BGA) 116 Table 70. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data 117 Table 71. LQPF100-14 x 14 mm 100-pin low-profile quad flat package mechanical data 118 Table 72. LQFP64-10 x 10 mm 64 pin low-profile quad flat package mechanical data 119 Table 73. Package thermal characteristics 120 Table 74. Ordering information scheme 123 6/130 Doc ID 1461 1 Rev 8 STM32F103xC, STM32F103XD. STM32F103XE List of figures List of figures Figure 1. STM32F103XC, STM32F103xD and stM32F103XE performance line block diagram..12 Figure 2. Clock tree Figure 3. STM32F103XC and STM32F103XE performance line BGA144 ballout ,,,,24 Figure 4. STM32F103xC and STM32F103XE performance line BGA100 ballout 25 Figure 5. STM32F103XC and STM32F103xE performance line LQFP 144 pinout Figure 6. STM32F103xC and sTM32F103xE performance line LQFP100 pinout 27 Figure 7. STM32F103XC and StM32F103xE performance line LQFP64 pinout ,,28 Figure 8. STM32F103XC and STM32F103XE performance line WLCSP64 ballout ball side 29 Figure 9 Memory map .38 Figure 10. Pin loading conditions 39 Figure 11. Pin input voltage ..39 Figure 13. Current consumption measurement scheme Figure 12. Power supply scheme 40 40 Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from ram, peripherals enabled ..46 Figure 15. Typical current consumption in Run mode versus frequency(at 3.6 v)- code with data processing running from RAM, peripherals disabled Figure 16. Typical current consumption on VBAT With RTC on Vs temperature at different VbaT values 8 Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different∨ Dp values,… ,,,,49 Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different Vpp values .50 Figure 19. Typical current consumption in Standby mode versus temperature at different Voo values Figure 20. High-speed external clock source AC timing diagram 56 Figure 21. Low-speed external clock source AC timing diagram ..57 Figure 22. Typical application with an 8 MHz crystal ,,,,58 Figure 23. Typical application with a 32.768 kHz crystal 60 Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 64 Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms 65 Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms 66 Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms 68 Figure 28. Synchronous multiplexed NOR/PSRAM read timings 69 Figure 29. Synchronous multiplexed PSRAM write timings 7 Figure 30. Synchronous non-multiplexed NOR/P SRAM read timings 73 Figure 31. Synchronous non- multiplexed PSRAM write timings 74 Figure 32. PC Card/CompactFlash controller waveforms for common memory read access Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read Ccess Figure 33. PC Card/ CompactFlash controller waveforms for common memory write access 76 access Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access 78 Figure 36. PC Card/CompactFlash controller waveforms for lo space read access 78 Figure 37. PC Card/CompactFlash controller waveforms for VO space write access 79 Figure 38. NAND controller waveforms for read access Doc ID 1461 1 Rev 8 7/130 List of figures STM32F103XC. STM32F103xD. STM32F103XE Figure 39. NAND controller waveforms for write access 81 Figure 40. NAND controller waveforms for common memory read access 81 Figure 41. NAND controller waveforms for common memory write access 82 Figure 42. Standard 1/0 input characteristics- CMOS port 87 Figure 43. Standard l/o input characteristics- TTL port 87 Figure 44. 5V tolerant 1/0 input characteristics- CMOS port 88 Figure 45. 5V tolerant l O input characteristics- ttl port 88 Figure 46. 1/0 AC characteristics definition 9 Figure 47. Recommended nrst pin protection Figure 48. 2C bus AC waveforms and measurement circuit 94 96 Figure 50. SP! timing diagram -slave mode and CPHA=1(1) ,96 Figure 51. SPI timing diagram -master mode(1) Figure 52. 12s slave timing diagram(Philips protocol) ( 1) Figure 53. 1-S master timing diagram(Philips protocol) 99 Figure 54. sdio high-speed mode 100 Figure 55. Sd default mode .100 Figure 56. USB timings: definition of data signal rise and fall time .....102 Figure 57. ADC accuracy characteristics .....105 Figure 58. Typical connection diagram using the ADC 翻 106 Figure 59. Power supply and reference decoupling(VREF+ not connected to VDDA 106 Figure 60. Power supply and reference decoupling(VREF connected to VdpA 107 Figure 61. 12-bit buffered /non-buffered dAc 109 Figure 62. BGA pad footprint Igure 63. LFBGA144-144-ball low profile fine pitch ball grid array, 10 X 10 mill ,112 Fic 0.8 mm pitch, package outli 113 Figure 64. LFBGA100-10X 10 mm low profile fine pitch ball grid array package outline 114 Figure 65. WLCSP, 64-ball 4.466 x 4.395 mm, 0.500 mm pitch wafer-level chip-scale package outline 115 Figure 66. BGA pad footprint 116 Figure 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline ,117 Figure 68. Recommended footprint (1) 117 Figure 69. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 118 Figure 70. Recommended footprint( 1) ..118 Figure 71. LQFP64-10 10 mm 64 pin low-profile quad flat package outline Figure 72. Recommended footprint (1) ...119 Figure 73. LQFP100 Pp max vs TA ,.122 8/130 Doc ID 1461 1 Rev 8 STM32F103xC. STM32F103XD. STM32F103XE Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103X C, STM32F103XD and STM32F103XE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2. 2: Full compatibility throughout the family The high-density stM32F103xx datasheet should be read in conjunction with the STM32F1OxXx reference manual For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10XXX Flash programming manual. The reference and Flash programming manuals are both available from the StmicrOeleCtronicswebsitewww.st.com For information on the Cortex TM-M3 core please refer to the Cortex TM-M3 Technical ReferenceManual,availablefromthewww.arm.comwebsiteatthefollowingaddress http:/intfocenter.armcom/help/indexjsp?topic=/com.armdoc.ddio337e/ Cortex Intelligent Processors by ARM ARMI Doc ID 1461 1 Rev 8 9/130 Description STM32F103XC, STM32F103xD. STM32F103XE Description The STM32F103XC, STM32F103XD and STM32F103XE performance line family incorporates the high-performance ARM Cortex TM-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced l /Os and peripherals connected to two APB buses. all devices offer three 12-bit ADCs, four general-purpose 16- bit timers plus two PWM timers, as well as standard and advanced communication interfaces:up to two 12Cs, three SPIs, two 12Ss, one SDIO, five USARTs, an USB and a CAN The STM32F103Xx high-density performance line family operates in the-40 to +105C temperature range, from a 2.0 to 3. 6V power supply. A comprehensive set of power-saving mode allows the design of low-power applications These features make the stM32F 1 03xx high-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCS, inverters, printers, scanners, alarm systems video intercom, and HVAC 10/130 Doc iD 1461 1 Rev 8

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