K3QF2F20EM-QGCE000_DRAM_216F 15x15_Ver

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智能手机的LPDDR3内存芯片。 Mobile DRAM Stack Specification 216FBGA, 15x15 8Gb DDP (256M x32) 2/CS, 2CKE + 8Gb DDP (256M x32) 2/CS, 2CKE
Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM Table of contents Mobile DRAM Stack Specification 10 COMPARISION BETWEEN LPDDR2 AND LPDDR3 6 20 KEY FEATURES 8 30 ORDERING INFORMATION 40 ADDRESS CONFIGURATION 5.0 PACKAGE dimension PIN DESCRIPTION 10 5. 1 LPDDR3 SDRAM Package Dimension 10 5.2 LPDDR3 SDRAM PACKAGE BALLOUT 5.3 PAD DEFINITION AND DESCRIPTION 5. 4 FUNCTIONAL BLOCK DIAGRAM 13 CHA 8Gb DDP LPDDR3 SDRAM(256M X32) 1.0 KEY FEATURE.….4 2.0 FUNCTIONAL BLOCK DIAGRAM 3.0 LPDDR3 PAD DEFINITION AND DESCRIPTION 5618 40 FUNCTIONAL DESCRIPTION 50 LPDDR3 SDRAM ADDRESSING 18 5. 1 Simplified lPddR 3 State Diagram 19 5.2 Mode register definition 5.2.1 Mode register Assignment and Definition in LPDDR3 SDRAM.... 6.0 TRUTH TABLES 6.1 Command truth table 27 6.2 CKE Truth table 29 6. 3 State Truth table 4 Data mask truth table 70 ABSOLUTE MAXIMUM RATINGS .33 8,0 ac DC OPERAtINg cOnditions 1 Recommended DC Operating Conditions....... 8.2 Input Leakage current 34 8.oPerating Temperature Range 9, AC AND DC INPUT MEASUREMENT LEVELS 9. 1 AC and dC Logic Input Levels for Single-Ended Signals 35 9.1.1 AC and dc input levels for single-Ended ca and cs n signals 35 2 AC and DC Input Levels for CKE 9.2. 1 AC and dc Input levels for single-Ended data signals 9. 3 Vref tolerances 36 4 Input Signal.… 37 5 AC and dc logic Input levels for differential signals 9.5.1 Differential signal definition 9.5.2 Differential swing requirements for clock(CK t-CK c)and strobe(DQs_t-DQsc) 39 9.5.3 Single-ended requirements for differential signals 40 9.6 Differential Input Cross Point Voltage ,41 9.7 Slew Rate Definitions for Single-Ended Input Signals 9. 8 Slew Rate Definitions for Differential Input Signals 42 10.0 AC AND DC OUTPUT MEASUREMENT LEVELS 43 10.1 Single Ended AC and dC Output Levels 43 10.2 Differential AC and DC Output Levels 43 10.3 Single Ended Output Slew Rate .44 10. 4 Differential Output Slew Rate 45 10.5 Overshoot and Undershoot Specifications 6 11.0 OUTPUT BUFFER CHARACTERISTICS 47 11.1 HSUL 12 Driver Output Timing Reference Load 47 120 RONPU AND R○ NPD RES| STOR DEF|NT|ON..…… 12.1 RoNPU and ronPd Characteristics with ZQ calibration 49 12.2 Output Driver Temperature and Voltage Sensitivity 49 AMSUN SAMSUNG ELECTRONICS Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM 12.3 RONPU and ronPd Characteristics without zQ calibration 0 2.4 RzQ I-V Curve 12.5 ODT Levels and l-v characteristics 13.0 INPUT/OUTPUT CAPACITANCE 140IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS 14.1 IDD Measurement Conditions 14.2 IDD Specifications 57 14.3 IDD Spec table 60 15.0 ELECTRICAL CHARACTERISTICS AND AC TIMING 62 15.1 Clock Specification 62 15.1.1 Definition for tcK(avg) and nCK 62 15.1.2 Definition for tCK(abs) 15.1.3 Definition for tCH(avg)and tCL(avg) 62 15.1. 4 Definition for tJiT(per) 62 15.1.5 Definition for jIT(cC)…… 15.1.6 Definition for tERR(nper 63 15. 1.7 Definition for duty cycle jitter tjiT(duty) 63 15.1.8 Definition for tCK(abs), tCH(abs)and tCL(abs) 5.2 Period clock jitter 64 15. 2. 1 Clock period jitter effects on core timing parameters 64 15.2.1.1 Cycle time de-rating for core timing parameters 15.2.1.2 Clock Cycle de- rating for core timing parameters 64 15.2.2 Clock jitter effects on Command/Address timing parameters 64 15.2.3 Clock jitter effects on Read timing parameters 65 15.2.3. 1 tRPRE .65 15.2. 3.2 tLZ(DQ), tHz(DQ), tDQSCK, tLZ(DQS), tHz(DQs) 65 15.2.3.3 tQSH. tQsL 65 15.2.3.4 tRUST 65 15. 2. 4 Clock jitter effects on Write timing parameters .65 152.4.1tDs,tDH. .65 15.2.4.2 tDSS tDSH 65 15.2.4.3 tDQSS 66 5.3 LP DDR3 Refresh Requirements by Device Density 154 AC Timing… 67 15.5 CA and cs n Setup, Hold and Derating 15.6 Data Setup, Hold and slew Rate Derating .... CHB 8Gb DDP LPDDR3 SDRAM(256M X32 10 KEY FEATURE 2.0 FUNCTIONAL BLOCK DIAGRAM 3.0 LPDDR3 PAD DEFINITION AND DESCRIPTION 87 4.0 FUNCTIONAL DESCRIPTION 88 5.0 LPDDR3 SDRAM ADDRESSING 5. 1 Simplified LPDDR3 State Diagram 5.2 Mode Register Definition 90 5.2.1 Mode Register Assignment and definition in LPDDR3 SDRAM 60 TRUTH TABLES 97 6. 1 Command truth table 97 6.2 CKE Truth table 6.3 State Truth table 100 6.4 Data mask truth table 102 70 ABSOLUTE MAXIMUM RATINGS 8.0 aC DC OPERATING CONDITIONs 104 8. 1 Recommended DC Operating Conditions 104 8.2 Input Leakage Current 104 8. 3 Operating Temperature Range 104 90 AC AND DC INPUT MEASUREMENT LEVELS 105 9. 1 AC and DC Logic Input Levels for Single-Ended Signals 9.1.1 AC and dc Input Levels for Single-Ended Ca and cs n Signals AMSUN SAMSUNG ELECTRONICS Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM 9.2 AC and dC Input Levels for CKE 105 9.2.1 AC and Dc Input Levels for Single-Ended Data Signals 3 Vref tolerances 9. 4 Input signal 9.5 AC and dC Logic Input Levels for Differential Signals 108 9.5.1 Differential signal definition 108 9.5.2 Differential swing requirements for clock(CK t-CK c)and strobe(DQs t-DQs c 9.5.3 Single-ended requirements for differential signals …110 9.6 Differential Input Cross Point Voltage.. 7 Slew Rate Definitions for Single-Ended Input Signals 112 9. 8 Slew Rate Definitions for Differential Input Signals 112 10.0 AC AND DC OUTPUT MEASUREMENT LEVELS 10.1 Single Ended Ac and dC Output Levels 113 10.2 Differential Ac and dc Output Levels 113 10.3 Single Ended Output Slew Rate 10.4 Differential Output Slew Rate 115 10.5 Overshoot and Undershoot specifications 116 11.0 OUTPUT BUFFER CHARACTERISTICS 117 11.1 HSUL 12 Driver Output Timing Reference Load 117 12.0 RONPU AND RONPD RESISTOR DEFINITION 118 12. 1 RoNPU and ronPd Characteristics with zQ Calibration 119 12.2 Output Driver Temperature and voltage Sensitivity 119 12.3 RoNPU and ronPd Characteristics without zQ calibration 120 12. 4 RZQ I-V Curve 121 12.5 ODT Levels and -v Characteristics 123 13.0 INPUT/OUTPUT CAPACITANCE …124 140 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS 125 14.1 IDD Measurement Conditions 125 14.2 IDD Specification 14.3 IDD Spec Table 130 15.0 ELECTRICAL CHARACTERISTICS AND AC TIMING 132 15.1 Clock Specification 132 15.1.1 Definition for tCK(avg)and nCK 15.1.2 Definition for tCK(abs) 15.1.3 Definition for tCH(avg) and tcL(avg) 15.1. 4 Definition for tIT(per) 15.1.5 Definition for tJIT(cc) 15.1.6 Definition for teRR(nper 133 15.1.7 Definition for duty cycle jitter tJIT(duty 133 15.1.8 Definition for tCK(abs), tCH(abs )and tCL(abs) 15.2 Period clock jitter 134 15.2. 1 Clock period jitter effects on core timing parameters... 134 15.2.1. 1 Cycle time de-rating for core timing parameters 15.2.1.2 Clock Cycle de-rating for core timing parameters 134 15.2.2 Clock jitter effects on Command/Address timing parameters 15.2.3 Clock jitter effects on Read timing parameters 135 15.23. 1 tRPRE 135 15.2.3.2 tLZ (DQ), tHz(DQ), tDQSCK, tLZ(DQs), tHz(DQs) 15.2.3.3 tOSH. tQSL 135 15.2.3.4 tRUST 135 15. 2.4 Clock jitter effects on Write timing parameters 15.2.4. tDS. tDH 135 15.2.4.2 tDSS tDSH 135 152.4.3 tDQSS. 5.3 LPDDR3 Refresh Requirements by Device Density 136 154 AC Timing… 137 155 CA and cs_ n Setup, Hold and derating…… 156 Data Setup, Hold and slew Rate Derating…… 148 AMSUN SAMSUNG ELECTRONICS Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM 10 COMPARISION BETWEEN LPDDR2 AND LPDDR3 Items LPDDR2 LPDDR3 CLK scheme Differential (CLK/CLKB) Data scheme DDR Single-ended Bi-Directional DQS scheme Differential(DQS/DQSB) Bi-Directional ADD/CMD scheme DDR State diagram Refer to the datasheet Command truth Table As No support BST State for bank n to bank n/m As is No support BST /Interrupt Feature Data mask Truth Table yo Interface HSUL 12 Burst Length 4( Default).8.16 8 Burst Type Sequential, Interleave Sequential Support(BL4) #t of Bank 8 16/×32 Data Mask Support (Write) Refresh mode All Bank Refresh/Per bank refresh Self Refresh R Colur Addressing(32) Refer to the datasheet Refer to the datasheet Bank Refresh Requirements Speed bin IMbpsl 667800/1066 16001866 Read/write latency Core Parameters AC Parameter O Parameters Refer to the datasheet Refer to the datasheet CA/ Cs n/ Setup/ Hold/ Deratin Data Setup/Hold /Deratin PASR lupo TCSR Support Deep Power Down No Support Configurable D/S Support Special Function ZQ Calibration Support DQ Calibration Support CA Calibratio N/A Support Write Leveling NA Support VDD1 V 1.70~1.95 VDD2 M 1.14~1.30 Power Supply VDDQ MVI 1.14-1.30 VDDCA V 1.14~1.30 IDD Specification Parameters and Test IDD Measurement Conditions Conditions IDD Specification As is General rC] Temperature Extended [c] 25~105 AMSUN SAMSUNG ELECTRONICS Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM Items LPDDR2 LPDDR3 General As is Support 2) Support MR1 BL/C/nWR) Support Mr2 RL &WL. nWRE2 Modified Mode register Set Support MR4 Refresh Rate rt (0.5×tREF|)2) Support MR8 l/O width, Type N/A MR41/4248 Adding N/A MR2 OP7 (Write Leveling) W/ZQ Calibration As is wio ZQ Calibration RONpU/RONpd Characteristics Temperature and voltage Sensitivity RzQ1-V Curve As is Input/Output Capacitance 3) VDD1Ⅳ -0.4~23 VDD2 M .4~1.6 DDQ MV -04~1.6 Absolute maximum DC ratings VDDCA TVI -0.4-1.6 VIN/VOUT M -0.4~1.6 Tstg [C] 55~125 Input leakage AC:VRE±0.150V/±0135V CA and cs n pins AC: VREF +/-022V (16001866) DC: VREF +/-013V DC:VREF±0.10V/±0.10V (16001866) AC/DC Logic Input Lev CKE pin 02× VDDCA-0.8× VDDCA els for Single-ended Sig nals Ac:VREF±0.15V AC: VREF +/-022V DQ pins ±0.135V(1600/1866) DC: VREF +/-013V C:VREF±0.10V/0.10V (1600/1866) VREF CA/DQ tolerance 0. 49xVDDQ-0.51xVDDQ AC/DC Logic Input Lev- VIHdiff/ILdiff(Ac/DC)tDVAC As is els for differential VSEH/VSEL(AC) As is Differential Input Cross VIXCAVIXDQ As is Input/Output Point Voltage Operating con- Slew Rate definitions for VILdiff /VIHdiff Differential (Max/Min) VOHdiff/voLdiff (ac) AC/DC Output levels for IOZ Differential MMPUPD AC/DC Output levels for VOHdiff /VOLdiff (ac) As is Differential Signal ended output VOH/VOL(AC!DC) Slew Rate ROSE Differential Output Slew ∨ OHdiff/oLdiff(AC As is SRQdiff Maximum amplitude Overshoot/Undershoot Maximum area VDD/VSS:0.1 MV-ns HSUL 12 Driver Output Timing NOTE 1)DQ out data are same in a byte 2)These items are modified from LPDDR2 sepcification, Please refer to Mode Register Definition s)The parameter applies to both die and package AMSUN SAMSUNG ELECTRONICS Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM LPDDR3 SDRAM SPECIFICATION Channel A: 8Gb DDP(256MX32)2/CS, 2CKE LPDDR3 SDRAM/ Channel B: 8Gb DDP(256MX32)2/CS, 2CKE LPDDR3 SDRAM 20 KEY FEATURES Double-data rate architecture; two data transfers per clock cycle Bidirectional data strobes(DQs t, DQs_ c), These are transmitted/received with data to be used in capturing data at the receiver Differential clock inputs(CK t and CK c) Differential data strobes (DQs t and DQs_c) Commands& addresses entered on both positive and negative CK edges data and data mask referenced to both edges of dQs 8 internal banks for concurrent operation Data mask(DM) for write data Burst Length: 8 Burst Type: Sequential Read Write latency: Refer to T able 45 LPDDR3 AC Timing Table Auto Precharge option for each burst access Configurable Drive Strength All Bank refresh. per bank refresh and self refresh Partial Array Self Refresh and Temperature Compensated Self Refresh Write Leveling CA Calibration HSUL-_12 compatible inputs ·VDD1/DD2 NDDO/VDDCA :1.8V1.2V12V/1.2V No DLL: CK to DQS is not synchronized Edge aligned data output, center aligned data input Operating Temperature: -25-85C On Die Termination using ODT pin 2/CS, 2CKE (Per channel) SAMSUNG AMSUN SAMSUNG ELECTRONICS Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM 3.0 ORDERING INFORMATION ax rrea Part Number Interface Package A-Channel B-Channel K3QF2F20EM-QGCF 1866Mbps(CK=1.075ns) 1866Mbps(CK=1.075ns) HSUL 12 15x15216FBGA K3QF2F20EM-QGCE 1600Mbps(tCK=1.25ns 600Mbps( tCK=1.25ns) K3QF2F2QEM· Q G CFICE Speed ausun CF: 1.075ns @RL14, tRCD18ns, tRP18ns Mobile dRAM Stack Memory CE:1.25nsaRL12, tRCD18ns, tRP18ns Device Type Temp Q: LPDDR3 LPDDR3 G:25~85°c( Standard A-Port W/F& Density vcc Org. F2. LPDDR3 4Gb+4G. VDD1=18V. VDD2=1.2V Package VDDQ=1.2V VDDCA=1.2V. X 32, 2/CS. 2CKE Q:15X15(216FBGA) B-port l/F density Vcc Org F2. LPDDR3 4G5+4Gb VDD1=18V VDD2=1.2V Generation VDDQ=1.2V VDDCA=1.2V. X32. 2/CS. 2CKE M: 1st Generati C-Port l/F Density Vcc Org Version 0. Reserve for future use E, E-die 44.0 ADDRESS CONFIGURATION Organization(A-Channel LPDDR3) Bank address Row Address Column address 256M×32 BAO-BA2 A0-A13 A0-A9 Organization(B-Channel LPDDR3) Bank Address Row Address Column Address 256MX32 BAO-BA2 A0-A13 A0-A9 AMSUN SAMSUNG ELECTRONICS 9 Rev 1.0 K3QF2F20EM-QGCF K3QF2F20EM-QGCE datasheet LPDDR3 SDRAM 5.0 PACKAGE DIMENSION Pin description 5.1 LPDDR3 SDRAM Package Dimension 216-Ball Fine pitch Ball Grid Array Package(measured in millimeters) 1500±0.10 Units millimeters 1 INDEX MARK TOP VIEW SIDE VIEW 0.74+00 0.50×28=1400 700 #Al INDEX MARK D05 2928272325242322212019181716154413121110987654321 Bc00000000c09000000000c000 C G H 00000 ccGcC W|C○ AA o000000000+000000O0O ooOOO AFCO O O AJc。 OOOOOOO。 COCOOOOOOOOOOCoo由 216-0 0. 3310.05 Post Reflow ( BOTTOM VIEW Solder Ball o0. 325) 40020MA B AMSUN SAMSUNG ELECTRONICS

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