################################################################################
# Vivado (TM) v2016.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
计算机组成原理课设要求做的54条cpu 用verilog HDL在vivado上编写的MIPS指令集的cpu,可以在N4板上下板运行,具体指令再实验报告和test文件夹中有 cputest文件夹是测试指令,在前仿真cpu时可以读取这些txt文件中的指令到内存中去,将结果输出到指定文件中,再与文件夹中的答案对比验证 用于前仿真的测试代码与最终的下板代码会有一点差异(关于频率和文件读写等),都是注释掉的,简单修改即可 两个实验报告中有比较详细的cpu设计图作为参考
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MIPS_54条指令CPU (583个子文件)
elaborate.bat 429B
compile.bat 317B
simulate.bat 279B
runme.bat 229B
runme.bat 229B
runme.bat 229B
cpu31.bit 3.65MB
in.coe 14KB
in.coe 14KB
in.coe 14KB
in.coe 14KB
in.coe 14KB
in.coe 14KB
in.coe 14KB
in.coe 14KB
in.coe 11KB
xsim.dbg 55KB
cpu31_routed.dcp 10.96MB
cpu31_placed.dcp 7.52MB
cpu31.dcp 3.91MB
cpu31_opt.dcp 3.29MB
iirom.dcp 94KB
iirom.dcp 94KB
hs_err_pid7076.dmp 103KB
hs_err_pid13420.dmp 96KB
compile.do 459B
compile.do 449B
compile.do 442B
compile.do 430B
simulate.do 325B
simulate.do 325B
simulate.do 320B
elaborate.do 192B
simulate.do 187B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
实验报告1.doc 1.99MB
实验报告.doc 1.08MB
CP0测试说明.docx 13KB
xsimk.exe 389KB
run.f 276B
usage_statistics_webtalk.html 30KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
xsim.ini 92B
xsim.ini 92B
vivado.jou 3KB
vivado_42388.backup.jou 1KB
vivado_66864.backup.jou 1KB
webtalk.jou 716B
webtalk_55612.backup.jou 716B
vivado.jou 618B
vivado_16736.backup.jou 605B
vivado_11680.backup.jou 605B
vivado.jou 605B
vivado_15448.backup.jou 605B
vivado_15564.backup.jou 605B
vivado_2400.backup.jou 604B
vivado.jou 600B
vivado_33596.backup.jou 600B
vivado_15488.backup.jou 600B
vivado_2248.backup.jou 599B
vivado_3684.backup.jou 590B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
vivado_42388.backup.log 71KB
runme.log 69KB
vivado_66864.backup.log 49KB
runme.log 36KB
runme.log 33KB
vivado.log 20KB
xvlog.log 5KB
compile.log 5KB
elaborate.log 3KB
xsimcrash.log 1KB
vivado_3684.backup.log 1KB
webtalk_55612.backup.log 956B
webtalk.log 956B
simulate.log 416B
xsimkernel.log 328B
exception.log 164B
hs_err_pid13420.log 143B
hs_err_pid7076.log 143B
cpu54.lpr 343B
xsim.mem 19KB
iirom.mif 46KB
iirom.mif 46KB
iirom.mif 46KB
iirom.mif 46KB
iirom.mif 46KB
iirom.mif 46KB
iirom.mif 46KB
iirom.mif 46KB
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