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This book defines the ARM-accessible registers of the MDM9X07/MDM8207/MDM9628 device. Registers are organized sequentially by address. The cores and their associated memory space are illustrated in Top-level memory map.NOTE Addresses in this document are offsets from zero.
Technical assistance For assistance or clarification on information in this document, submit a case to Qualcomm TechnologiesInc.(Qtiathttps:/support.cdmatech.com/.Ifyoudonothaveaccesstothe CDMATech Support Service website, register for access or send email to support. cdmatechaqualcomm com Revision history Bars appearing in the left margin(as shown here) indicate where technical changes have occurred for this revision The following tables list the technical content changes for all revisions Revision a. november 2015. initial release Revision B, December 2015 initial release to customer 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION Contents 1 Introduction 1.1 Overview 1.2 Definitions/guidelines 7778 1.3 Register categories 1.4 Memory map 1.5 Register definitions. 2 GCC GLOBAL CLK CTL REG 3DMc00 DDRPHY CA………"o……………… 340 4DMD00_ DDRPHY DQ.…… 364 5 DIM DO1 DDRPHY DQ.. ■m■ 385 6 DIM DO2 DDRPHY DQ 407 7 DIM D03 DDRPHY DQ …429 8 LPASS LPA F …………………,451 9 QDSS DAPROM 506 10 QDSS QDSSCSR. 11 QDSS CXSTM 2 3232 TRUE 543 12 QDSS CTIO CSCTI 564 13 QDSS CT1CSCT.…1572 14 QDSS CTI2 CSCTI. 15 QDSS CT3 CSCTI .588 16 QDSS CTI4 CSCTI. 17 QDSS CT5 CSCTI 604 18 QDSS CTI6 CSCTI 重B口日题 n612 19 QDSS CTI7 CSCTI 620 20 QDSS CT8 CSCTI ■Bl 28 21 QDSS CSTPIUCSTPIU. 22 QDSS IN FUNO CXATBFUNNEL 128W8SP 656 23 QDSS REPL64 CXATBREPLICATOR 64WP 673 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U S, AND INTERNATIONAL EXPORT CONTROLLED INFORMATION MDM9XO7/MDM8207/MDM9628 Hardware Register Description For OEMs Contents 24 QDSS ETFETB CXTMC F128W8K 684 25 QDSS ETR CXTMC R64W32D 704 26 QDSS NDPBAM BAM 1723 27 SECURITY CONTROL CORE 764 28 SECURE CHANNEL 28.1 CRI CM 864 28.2CR|CMEⅩT 864 29 TLMM CSR 865 30 BLSP1 BLSP UARTO UART DM 重量重日量b重圆 B圆B ……897 31 BLSP1 BLSP UART1 UART DM.mammon, 936 31.1 UART DM registers ..936 32 BLSP1 BLSP UART2 UART DM 975 33 BLSP1 BLSP UART3 UART DM1014 34 BLSP1 BLSP UARTA UART DM ■日口口国B圆重B 1053 35 BLSP1 BLSP UART5 UART DM n1092 36USB2HS|CUSB0TGHS∴1131 37 USB2 PHY CM DWC USB2 …1205 38 USB OTG HS mnmmmERSRSn 1234 39 USB OTG HS BAM ………1308 40 QPIC EBI2CR 1349 41 QPIC EBI2ND..... BunGeE 1365 41.1 QPIC MPU1132 8 M39L 16 AHB 40 1447 42 QPIC BAM LITE TOP QPIC 42.1 QPIC QPIC XPU2 1486 42.2 QPIC QPIC VMIDMT 1486 43 EMAC 0 EMACEMAC 1487 44 EMAC 0 EMACEMAC CSR 1567 45 EMAC 0 EMAC EMAC 1588 1577 46 EMAC 0 SGMII 1651 46.1 EMACO EMAC QSERDES TXTX 1663 46.2 EMAC 0 EMAC QSERDES RX RX 1671 46.3 EMAC O EMAC SGMII PHY 1687 47 SDC1 SDCC SDCC5 1714 48 SDC1 SDCC SDCC5 HC 1760 49 SDC2 SDCC SDCC5 1809 50 SDC2 SDCC SDCC5 HC 1855 51BLsP1BLsP_QUP0_QUP…… 1904 52 BLSP1 BLSP QUP1 QUP …1928 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U S, AND INTERNATIONAL EXPORT CONTROLLED INFORMATION MDM9XO7/MDM8207/MDM9628 Hardware Register Description For OEMs Contents 53 BLSP1 BLSP QUP2 QUP 1952 54 BLSP1 BLSP QUP3 QUP 1976 55 BLSP1 BLSP QUP4 QUP 2000 56 BLSP1 BLSP QUP5 QUP. 57 QDSS WRAPPER QDSS WRAPPER.....………2048 58 QDSS WRAPPER ATB FUN2X1 CXATBFUNNEL 32W2SP 58.1 cXatbfunnel 32W2sp Registers 2057 Index of Registers .mmm 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 1 Introduction 1.1 Overview This book defines the ARM-accessible registers of the MDM9XO7/MDM8207/MDM9628 device Registers are organized sequentially by address. The cores and their associated memory space are llustrated in Top-level memory map note Addresses in this document are offsets from zero 1.2 Definitions/guidelines Table l-l offers guidance in interpreting the register definitions and covers some of the issues and ssumptions made throughout this book Table 1-1 Register definitions Guidelines Endian is a term that defines the byte order to store a sequence of bytes in memory Endian either MSB first(big-endian)or LSB first(little-endian) Hardware coding defines MDM byte registers; in each 32-bit word, MSB=31, LSB=0. The MDM chips support only little order endian addressing. In little endian mode, the first byte is bits 7: 0, and the fourth byte is bts31:24 All registers are word-accessible Assume the ArM convention a byte, 8 bits a half word, 16 bits; a word, 32 bits. All accesses are expected to be word size. The aRM can Word do byte and halt-word reads, since hardware treats a read as a word access. Individual addressing bytes accesses to a read register that triggers a hardware event will trigger an event for each read performed Active Unless stated otherwise, all boolean flags are active-high in register descriptions. Use a value of 1"to enable a function or indicate an event and a value of "o"do the opposite bit Active-low flags are explicitly specified in the register descriptions For example, if the state booGa EnA bit is set 1. it enables booga mode: if cleared o. it disables the mode In the register map many bits are marked RESeRVEd or unused ignore undefined bits in readable registers, software cannot assume a0 upon a read Write undefined Unused bits with'O's' in writable registers. Bits marked"IGNORED"can be written with any bits/ desired value: in some cases this is convenient to software words MDM memory and register addressing simplifies implementation and allows expansion lany holes exist in the address space. Avoid accesses to undefined memory locations they can cause unpredictable behavior 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U S, AND INTERNATIONAL EXPORT CONTROLLED INFORMATION MDM9XO7/MDM8207/MDM9628 Hardware Register Description For OEMs Introduction Table 1-1 Register definitions(cont Guidelines A registers reset state is 'unknown' unless stated otherwise. It's better not to use a Reset reset in hardware, it conserves area and simplifies coding and testing. Bits with a reset state ill be noted in the register descriptions. Assume that when a core comes out of reset all its programmed register bits are either in their reset state(where defined)or unknown Do not expect a previously programmed value to be maintained 1.3 Register categories Most registers can be categorized using one of the types listed in Table 1-2. These categories are defined here to simplify the software interface Table 1-2 Register categories Guidelines Command registers are always write-only, typically there is no meaningful read- back value Use command registers to trigger events in the hardware. Often these registers serve a single purpose. You write a bit pattern to specify the desired event. multiple Write events can be combined; a register may have multiple 1-bit fields, each field triggering command a hardware action, such as in an interrupt clear register A command register can also contain encoded command fields and other data fields The bit pattern written to it is transient; i.e there is no need to first write a value to trigger the event and another value to stop the event. If this is not the case, it will be SO-stated in the register definition These registers return the desired data, but may also trigger a hardware event every R time they are read. Often they are used to read out memory locations where each command read triggers a read of the next memory location Control registers configure the hardware to operate in a specific mode. These Control registers are either static or take effect at a specific time boundary (such as the next 256 chip boundary ) Control bits are registered in hardware and may be readable Status registers are read-only and reflect the current state of the hardware. There Status may be restrictions on when the status words can be reliably read, this ensures a self consistent value is available. Any restrictions will be indicated in the register descriptions State registers are read/writable by the processor but also change state due to hardware events. For software to reliably read or update a state register, special State rules of engagement" may be needed to read out a self-consistent value or avoid collisions for updates by software and hardware. Each state register has these rules described in detail Abbreviations W write register read register RCx command register unknown after power-on 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION MDM9XO7/MDM8207/MDM9628 Hardware Register Description For OEMs Introduction 1.4 Memory map 0x100000000 DDR (3 GB) 0×40000000 64B什 T CATS(512MB) 0X20000000 Reserved (334 MB 0x0B200000 A7SS (2 MB) 0×0B000000 (16MB) 0x0A000000 QDSS STM(16 MB) 0x09000000 R d (8 MB) 0x08802000 0x08801000 Reserved (4 KB LEGEND Reserved (2 MB) 0x08604000 0x08600000 SYSTEM_ IMEM(16 KB) Memory Reserved(4 MB) 0×08200000 Mixed Reserved(2 MB) 0x08000000 Reserved PCNOC(2 MB 0×00000000 Figure 1-1 Top-level memory map 1.5 Register definitions All addresses pertain to the arm All non-command writable registers may have a reset condition as well as a time when the write takes effect. by default, writable registers do not have a reset condition and a value written takes effect immediately. Registers not following the default behavior use the notation below 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U S, AND INTERNATIONAL EXPORT CONTROLLED INFORMATION MDM9XO7/MDM8207/MDM9628 Hardware Register Description For OEMs Introduction Reset State: The value this register contains following a reset Each register also specifies the clock regime it is on Clock: <main regime> <local regime> This information can be used by software to determine the main and/or local regime that a register is part of. Reads and writes to registers where the clock regime is disabled are not supported Although the device will not hang-up when clocks are disabled, there is no guarantee the access will take place. Software can find where this condition may be an issue by enabling aborts for that type of access 80-P1511-2XRev.B Confidential and Proprietary-Qualcomm Technologies, Inc MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

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