ARMv7M参考手册

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ARMv7M是arm架构下最新架构,具有十分卓越的处理能力。
4. No licence, express, implied or otherwise, is granted to LICENSEe, under the provisions of clause 1, to use the arm tradename, in connection with the use of the arm architecture Reference manual or any products based thereon Nothing in Clause l shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM Architecture Reference Manual or any products based thereon. Where the term ARM is used to refer to the company it means"ARM or any of its subsidiaries as appropriate 110 Fulbourn Road Cambridge, England CBl 9NJ Restricted rights Legend Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in dFArs 252.227-7013(c)(1)(ii) and FAr 52.227-19 This document is Non-Confidential. The right to use, copy and disclose this document is subject to the licence set out ARM DDI 0405C Copyright C 2006-2008 ARM Limited. All rights reserved. Unrestricted Access Non-Confidentia/ Copyright o 2006-2008 ARM Limited. All rights reserved ARM DDI 0405C Non-Confidentia Contents ARMV7-M Architecture Application Level Reference Manual Preface about this manu XVI Using this manual Conventions Further reading XX Feedback XXI Part a Application Level Architecture Chapter A1 Introduction A1.1 The ARM Architecture-m profile A12 Chapter A2 Application Level Programmers'Model A2 About the application level programmers' model A22 A2.2 ARM core data types and arithmetic A23 A2.3 Registers and execution state ....... .A2-11 A2. 4 EXceptions, faults and interrupts .A2-15 A2.5 Coprocessor support ∴A2-16 ARM DDI 0405C Copyright C 2006-2008 ARM Limited. All rights reserved. Unrestricted Access Non-Confidentia/ Contents Chapter A3 ARM Architecture Memory Model A3. 1 Address space A3-2 A3.2 Alignment support .A3-3 A3.3 Endian support A3-5 A3. 4 Synchronization and semaphores A3-9 A3.5 Memory types and attributes and the memory order model .... A3-19 A3.6 Access rights A3.7 Memory access order……… A3-31 A3.8 Caches and memory hierarchy A3-39 Chapter a4 The aRMv7-M Instruction Set A4, 1 About the instruction set A4-2 A42 Unified Assembler Language…… A4-4 A4.3 Branch instructions A4-7 A4.4 Data-processing instructions A4-8 A4.5 Status register access instructions .A4-15 A4.6 oad and store instructions A4-16 A4.7 Load/store multiple instructions A4-19 A4.8 Miscellaneous instructions ∴A4-20 A49 Exception- generating instructions……… A4-2 A4.10 Coprocessor instructions……………………A4-22 Chapter A5 Thumb Instruction Set Encoding A5.1 Thumb instruction set encoding A5-2 A52 16-bit Thumb instruction encoding .A5-5 A5.332- bit Thumb instruction encoding…… .A5-13 Chapter A6 Thumb Instruction Details A6.1 Format of instruction descriptions .A6-2 A6.2 Standard assembler syntax fields A6-7 A6.3 Conditional execution A6-8 A6.4 Shifts applied to a register A6-12 A6.5 Memory accesses……….….…..………A6-15 A6 6 Hint Instructions A6-16 A6.7 Alphabetical list of ARMV7-M Thumb instructions A6-17 Part B System Level Architecture Chapter b1 System Level Programmers'Model B1. 1 Introduction to the system level B1-2 B1.2 System programmers' model B13 Chapter B2 System Address Map B2. 1 The system address map B2-2 B2.2 System Control Space(SCS) B2-6 Copyright C 2006-2008 ARM Limited. All rights reserved ARM DDI 0405C Non-Confidentia B2.3 System timer- Sys Tick ..B2-8 B2.4 Nested Vectored Interrupt Controller(NVIC) .B2-9 B2.5 Protected Memory System Architecture B2-12 Chapter B3 ARMV7-M System Instructions B3. 1 Alphabetical list of ARMv7-M system instructions B3-2 Part c Debug Architecture Chapter C1 ARMv7-M Debug C11 Introduction to debug C1-2 C12 The Debug Access Port(DAP)………………… C1-4 C1.3 Overview of the ARMv7-M debug features C1-8 C1.4 Debug and reset C1-11 C1.5 Debug event behavior C1-12 C1.6 Debug register support in the SCs ∴C1-16 C1.7 Instrumentation Trace Macrocell(ITM) support C1-17 C1.8 Data Watchpoint and Trace(DWT) support .C1-19 C1. 9 Embedded Trace(ETM) support ∴C1-2 C1. 10 Trace Port Interface Unit (TPlU B面面面B国面面 C122 C1. 11 Flash Patch and Breakpoint(FPB)support ..C1-23 Appendix a CPUID Core Feature ID Registers AppxA-2 Appendix B Legacy Instruction Mnemonics B.1 Thumb instruction mnemonics AppxB-2 B.2 Pre-UAL pseudo-instruction NOP ……… AppXB6 Appendixc Deprecated Features in ARMV7-M Appendix d Pseudocode definition D.1 Instruction encoding diagrams and pseudocode………….. AppXD2 D2 Limitations of pseudocode AppxD-4 D3 Data Types Appx D-5 D.4 Expressions AppXD-9 D.5 Operators and built-in functions AppxD-11 D 6 Statements and program structure Appx D-17 Miscellaneous helper procedures and functions AppxD-22 Glossary ARM DDI 0405C Copyright C 2006-2008 ARM Limited. All rights reserved. Unrestricted Access Non-Confidentia/ Copyright C 2006-2008 ARM Limited. All rights reserved ARM DDI 0405C Non-Confidentia List of tables ARMV7-M Architecture Application Level Reference Manual Change History… 面面面面 国国面面面自面面面面面国面 Table a3-1 Little-endian byte format A3-5 Table a3-2 Big-endian byte format A3-5 Table a3-3 Little-endian memory system .A3-6 Table a3-4 Big-endian memory system A3-6 Table a3-5 Load/store instructions and element size association A3-7 Table a3-6 Effect of Exclusive instructions and write operations on local monitor.... A3-11 Table A3-7 Effect of load/store operations on global monitor for processor(n) A3-15 Table a3-8 Memory attribute summary A320 Table a4-1 Branch instructions A4-7 Table a4-2 Standard data-processing instructions .A4-9 Table a4-3 Shift instructions A4-10 Table a4-4 General multiply instructions A4-11 Table a4-5 Signed multiply instructions A4-11 Table a4-6 Unsigned multiply instructions .A4-11 Table a4-7 Core saturating instructions A4-12 Table a4-8 Packing and unpacking instructions A4-13 Table a4-9 Miscellaneous data-processing instructions A4-14 Table a4-10 Load and store instructions A4-16 Table a4-11 Load/store multiple instructions A4-1 Table a4-12 Miscellaneous instructions A4-20 ARM DDI 0405C Copyright C 2006-2008 ARM Limited. All rights reserved. X Unrestricted Access Non-Confidentia/ ist of tables Table a5-1 16-bit thumb instruction encoding .... A5-5 Table a5-2 16- bit Thumb encoding………… .A5-6 Table a5-3 16-bit Thumb data processing instructions A5-7 Table a5-4 Special data instructions and branch and exchange A5-8 Table a5-5 16-bit Thumb Load/store instructions A5-9 Table A5-6 Miscellaneous 16-bit instructions A5-10 Table A5-7 If-Then and hint instructions A5-11 Table A5-8 Branch and supervisor call instructions A5-12 Table A5-9 32-bit Thumb encoding .A5-13 Table A5-10 32-bit modified immediate data processing instructions A5-14 Table a5-11 Encoding of modified immediates in Thumb data-processing instructions. A5-15 Table A5-12 32 bit unmodified immediate data processing instructions……………A5-17 Table a5-13 Branches and miscellaneous control instructions ................ A5-18 Table a5-14 Change processor state and hint instructions A5-19 Table a5-15 Miscellaneous control instructions A5-19 Table A5-16 Load/store multiple instructions ∴A5-20 Table a5-17 Load/store dual or exclusive, table branch wwwwwwwww A5-21 Table A5-18 Load word∴ A5-22 Table a5-19 Load halfword A5-23 Table A5-20 Load byte, preload……… ∴A5-24 Table a5-21 Store single data item A5-25 Table a5-22 Data- processing( shifted register)…… A5-26 Table a5-23 Move register and immediate shifts A5-27 Tab|eA5-24 Data processing(register)……… A5-28 Table a5-25 Miscellaneous operations A5-29 Table A5-26 Multiply and multiply accumulate operations .A5-30 Table a5-27 Long multiply, long multiply accumulate, and divide operations A5-31 Table a5-28 Coprocessor instructions …A5-32 Table A6-1 Condition codes A6-8 Table a6-2 Effect of iT execution state bits A6-11 Table A6-3 Determination of mask field A6-79 Table A6-4 MOV(shift, register shift)equivalences) A6-152 Table b1-1 Mode, privilege and stack relationship B1-4 Table B1-3 iCI/T bit allocation in the eps....... Table b1-2 The xPSR register layout …B1-7 B1-8 Table b1-4 The special-purpose mask registers B1-9 Table b1-5 Exception numbers B1-13 Table b1-6 Vector table format B1-14 Table b1-7 Exception return behavior B1-17 Table b2-1 ARMV7-M Address map B23 Table b2-2 SCS address space regions B2-6 Table C1-1 PPB debug related regions C1-3 Table c1-2 ROM table entry format .C1-4 Table c1-3 ARMV7-M DAP accessible rom table C1-4 Table c1-4 Debug related faults c1-12 Table c1-5 Debug stepping control using the DHSCR………… ∴C1-14 Table C1-6 Debug register region of the SCS C1-16 Copyright o 2006-2008 ARM Limited. All rights reserved ARM DDI 0405C Non-Confidentia

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