EM63A165TS-6G_datasheet.pdf

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CLK Input CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers CKE Input CKE activates(HIGH) and deactivates(LOW) the CLK signal CKE goes low synchronously with clock (set-up and hold time same as other inputs),the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standb BAO,BA1 Input BAO, BA 1 input select the bank for operation BA1 BAO Select bank 0 0 BANK #A BANK #B BANK #C 1 BANK #D A0-A12 Input A0-A11 are sampled during the BankActivate command (row address AO-A11)and Read/Write command(column address AO-A8 with A10 defining Auto Precharge)to select one location out of the 4M available in the respective bank. During a Precharge command, A10 is sampled to determine all banks are to be precharged(A10=HIGH). The address inputs also provide the op-code during a Mode Register Set command CS# pu CS# enables (sampled LoW) and disables (sampled HIGH)the command decoder. All commands are masked when CS# is sampled HIGH. CS# rovides for external bank selection on systems with multiple banks. It is considered part of the command code RAS# Input The RAS# signal defines the operation commands inl Conjunction with the CAS# and WE# signals and is latched at the positive edges of clK. When rast and CS# are asserted Low"and CAs# is asserted HIGH, either the BankActivate command or the Precharge command is elected by the WE# signal. When the WE# is asserted"HIGH,"the BankActivate command is selected and the bank designated by bs is turned on to the activel state. When the WE# is asserted "LOW, the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. CAS# Input The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges f clk. when rastt is held "HIGH and Cs#t is asserted " low. the column access is started by asserting cast"low. then the read or Write command is selected by asserting WE#"LOW"or"HIGH 3 Rev 1. 1 Apr 2007 WE# Input The WE# signal defines the operation commands in conjunction ith the RAS# and CAS# signals and is latched at the positive edges of CLK. the E# input is used to select the BankActivate or Precharge command and Read or Write command LDQM Controls output buffers in read mode and masks UDQM Input data in write mode DQ0-DQ15 Input/ The dQ0-15 input and output data are synchronized with the positive Output edges of CLK. The l/Os are maskable during Reads and Writes NCIRFU These pins should be left unconnected Supply Provide isolated power to DQs for improved noise immunity 3.3V±0.3V) SSQ Supply Provide isolated ground to DQs for improved noise immunity (0V) DD Supply +3.3V±0.3V Vss Supply Re1.1Apr.2007 Fully synchronous operations are performed to latch the commands at the positive edges of CLK Table 2 shows the truth table for the operation commands Ban aCtivate Idle(3) V Row address L L H BankPrecharge Any L LL L PrechargeAll Any LL L Write Active(3) H V「L| Column H L L Write and AutoPrecharge Active(3) H X×V H address (AO-A8)LH Read Active(3) H VL Colu L H address Read and Autoprecharge Active(3) H X H(AO-A8)LH Mode Register Set Idle H oP code No-Operation HLH Any Burst Stop Active(4) H ×| L Device deselect Any H X X Auto Refresh Idle L SelfRefresh Entry Idle L LL L SelfRefresh Exit Idle H× SelfRefresh) H Clock Suspend Mode Entry Active L XX×X×| Power Down Mode Entry Any(5) H xX X×X Clock Suspend Mode Exit Active L X×××X| XHHXHXXHXXHX H×× PowerDown) Data Write/Output Enable Active Data Mask/Output Disable Active H ×××|X 1.V=Valid X=Don ' t Care L=Low level h=high level 2. CKEn signal is input level when commands are provided CKEn-1 signal is input level one clock cycle before the commands are provided 3. These are states of bank designated by Bs signal 4. Device state is 1, 2, 4, 8, and full page burst operation 5. Power Down Mode can not enter in the burst operation When this command is asserted in the burst cycle device state is clock suspend mode Rev 1. 1 Apr 2007 1 BankActivate (RAS#="L", CAS#="H, WE#="H". BAS=Bank, A0-A12= Row Address) The BankActivate command activates the idle bank designated by the BA0, 1 signals. By latching the row address on A0 to A12 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRcD(min. )from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged(refer to the following figure The minimum time interval between successive bankActivate commands to the same bank is defined by tRc(min. The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks tRRD(min specifies the minimum time required between activating different banks. After this command is used, the Write command and the block Write command perform the no mask write operation TO T2 Tn+4 Tn+6 BanK a Bank A Bank B Bank A Col Addr RAS#I- CAS# delay (tRCD RAS#L RAS# delay time (tERD) NOP Bank B Activa OPted harg Activ NOP NOP Activate RAS# Cycle time(tRc) Auto Precharge 2 BankPrecharge command (RAS#=L, CAS#=H",WE#=L, BAS= Bank, A10=L, A0-A9, A11 and A12= Dont care) The BankPrecharge command precharges the bank disignated by ba signal. The precharged bank is switched from the active state to the idle state. this command can be asserted anytime after tRAs(min. )is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAs(max ) Therefore, the precharge function must be performed in any active bank within tRAs(max ) At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again 3 PrechargeAll command (RAS#="L", CAS#="H",WE#="L", BAS= Dont care, A10="H", A0-A9, A11 and A12= Don't care) The PrechargeAll command precharges all banks simultaneously and can be issued even if al banks are not in the active state. all banks are then switched to the idle state 4 Read command (RAS#="H", CAS#="L", WE#="H", BAS= Bank, A10="L", A0-A8= Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRcD(min. ) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the read command. Each subsequent data-out element will be valid by the next positive clock edge(refer to the following figure). The dQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue) 6 Rev 1. 1 Apr 2007 To T2 T5 READ A NOP NOP NOP NOP NOP NOP DOUT AO OOUT A, Y DOUT A2 DOUTA DOUTA DOUT A2 XDOUT A3 The read data appears on the das subject to the values on the dQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent read or Write command to the same bank or the other active bank before the end of the burst length It may be interrupted by a Bank Precharge/ Precharge All command to the same bank too. The interrupt coming from the read command can occur on any clock cycle following a previous Read command (refer to the following figure) T1 T6 T7 个LF1L fLfL READ A DOUT AO XDOUT Bo DOUT B. DOUT DOUT B3 DOUTA DOUTB DOUTB, XDOUT DOUT B3 The dQM inputs are used to avoid lo contention on the dQ pins when the interrupt comes from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins To guarantee the DQ pins against 1/0 contention, a single cycle with high-impedance on the dQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted(HiGH) at least one clock prior to the Write command to avoid internal bus contention TO T1 T6 T7 ( NOP R READ AX NOP N NOP NOP NOP \WRITE B NOP NOP DOUT DINBo DINB DINB lust be Hi-Z before the Write command Rev 1. 1 Apr 2007 T 〈NP)NP)(絲) NOP READ A RITE A NOP NOP NOP DIN AO din a DIN A DIN A TO T 1 T2 T3 T5 T6 T7 〈NP)(REcA)(Np)(Np)waEB)、Nop) NOP NOP DIN BO DNB1 DIN Bo IN B3 A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ Precharge All command is issued in different CAS# latency TO READ A NOP NOP Precharge NO NOP Activate NOP DOUT Ao DOUT A1 XDOUT A2 DOUTA DOUTA 0 DOUTA XDOUT A 5 Read and Auto Precharge command (RAS#="H", CAS#="L", WE#="H", BAS= Bank, A10=H, A0-A8= Column Address) 8 Rev 1. 1 Apr 2007 The Read and auto Precharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of [tRP(min. ) burst length). At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored 6 Write command (RAS#="H", CAS#="L, WE# ="L, BAS= Bank, A10=L, A0-A8= Column Address The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank the bank must be active for at least tRcD(min before the Write command is issued During write bursts the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue) To T2 T6 T8 fLt WRITEA NOP NOP DIN Ao DIN A DIN A2 Din A dont care The first data element and the write Extra dala is masked are registered on the same clock edge a write burst without the auto precharge function may be interrupted by a subsequent Write BankPrecharge/PrechargeAll, or Read command before the end of the burst length An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure) NOP WRITE A WRITE NOP NOP NOP NOP 1 Clk Interval DIN DIN Bo DIN B2 DIN B 3 The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed Rev 1. 1 Apr 2007 TO T4 T5 T8 NOP WRITE A READ NOP NOP NOP NOP NOP DIN Ao dont care DOUT DOUTB DOUT B2 DOUT B3 DIN Ao don't e don't ca OUT Bo X DOUTB1XDOUT DOUT B3 Input data must be removed from the dQs at least one clock Input data for the write is masked. cycle before the Read cala appears an the outputs to avad data contention 10 Re1.1Apr.2007

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