MTK6589规格书

所需积分/C币:9 2014-07-01 10:34:04 1.4MB PDF
17
收藏 收藏
举报

MTK6589规格书,详细地描述了MTK6589芯片的性能和架构,值得一看
MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A Table of contents D。 cument Revision History.,,,,… Tab| e of contents,,… System Overview 1.1 Platform Features 1.2 MODEM Features 1.3 Multimedia features 1.4 General Descriptions 2 Product Description.,,,,…,…,… 12 2.1 Pin Description 21.1 Ball Map view.… 12 2.1.2 Pin Coordinate 13 2.1.3 Detailed Pin Description 2.2 Electrical Characteristic 29 2.2. 1 Absolute Maximum Ratings 2.2.2 Recommended Operating Conditions.……… 2.2.3 Storage Condition.…….…… 2.2.4 AC Electrical Characteristics and Timing Diagram 31 2.3 System Configuration.…… 34 2.3.1 Mode selection 34 2.3.1 Constant Tie pins 2.4 Power-on Sequence 35 2.5 Analog Baseband 2.5.1 BBRX 37 2.5.2 BBTX ,,,,, 39 2.5.3 2GBBTⅩ 2.5.4 APC-DAC 42 2.5.5 VBIAS-DAC 43 2.5.6 AUXADC 2.5.7 Clock Squarer 1。i 2.5.8 Phase Locked Loop 46 2.5.9 Temperature Sensor…… 51 2.6 Package Information 52 2.6.1 Package Outlines …52 2.6.2 Thermal Operating Specifications 52 2.6.3 Lead-free Packaging 52 2.7 Ordering Information 53 2.7.1 Top Marking Definition 53 Mediatek confidential @2012 Mediatek Inc Page 3 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A List of Figures Figure1-1: Block diagram of MT6589.…… Figure 2-1: Ball map view of MT6589.......... Figure 2-2: Basic timing parameter for LPDDR2 commands Figure 2-3: Basic timing parameter for LPDDR2 write 32 Figure 2-4: Basic timing parameter for LPDDR2 read 33 Figure 2-8: Power on/off sequence with XTAL..... 35 Figure 2-9: Power on/off sequence without XTAL Figure 2-10: Block diagram of BBRX-ADC 38 Figure 2-11: Block diagram of 2GBBTX 4 Figure 2-12: Block diagram of APC-DAC Figure 2-13: Block diagram of VBlAS-DAC 43 Figure 2-14: Block diagram of AUXADC 44 Figure 2-15: Block diagram of Pl Figure 2-16: Outlines and dimensions of FCCSP 118mm*118mm, 515-ball,0. 4mm pitch package. 52 Figure 2-17: Top mark of MT6589 List of tables Table 2-1: Pin coordinate 13 Table 2-2: Acronym for pin type Table 2-3: Detailed pin description 17 Table 2-4: Absolute maximum ratings for power supply 9 Table 2-5: Recommended operating conditions for power supply Table 2-6: LPDDR2 AC timing parameter table of external memory interfaces.......... .33 Table 2-8: Mode selection of chip(PMU 6320 pin) 34 Table 2-9: Constant tied pins of MT6589 34 Table 2-10: Baseband downlink specifications ∴38 Table 2-11: Baseband uplink transmitter specifications ............. Table 2-12: Baseband uplink transmitter specifications aaa.:::::aaaaaaaaaa::::::aaaaaa:a 41 Table 2-13: APC-DAC specifications Table 2-14: VBlAS-DAC specifications Table 2-15: Definitions of auxadc channels 44 Table 2-16: AUXADC specifications 45 Table 2-17: Clock squarer 1 &2 specifications 46 Table 2-18: ARMPLL specifications …47 Table 2-19: MAINPLL specifications 48 Table 2-20: MMPLL specifications Table 2-21: ISPPLL specifications 48 Tabe2-22:∪ NIVPLL specifications… 49 able 2-23: MSDCPLL specifications Table 2-24: TVDPLL specifications Table 2-25: LVDSPLL specifications Table 2-26: MDPLL1& MDPLL2 specifications Table 2-27: WPLL specifications Table 2-28: WHPLL specifications Table 2-29: MCUPLL1 MCUPLL2 specifications 51 Table 2-30: Temperature sensor specifications Table 2-31: Thermal operating specifications 52 Mediatek confidential @2012 Mediatek Inc Page 4 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A Mediatek confidential @2012 Mediatek Inc Page 5 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A 1 System Overview MT6589 is a highly integrated baseband platform incorporating both modem and application processing subsystems to enable 3G smart phone applications. The chip integrates a Quad-core ARMO Cortex-A7 MPCore operating up to 1.2GHZ, an ARM Cortex-R4 MCU and a powerful multi- standard video accelerator. The MT6589 interfaces to NAND flash memory, 32-bit LPDDR2 for optimal performance and also supports booting from SLC NANd or eMmc to minimize the overall BOM cost. In addition, an extensive set of interfaces and connectivity peripherals are included to nterface to cameras, touch-screen displays, MMC/SD cards and external Bluetooth, WiLaN and GPs modules The application processor, a Quad-core aRme Cortex-A7 MPCorsTM which includes a neon multimedia processing engine, offers processing power necessary to support the latest OpenOs along with its demanding applications such as web browsing, email, GPS navigation and games. All are viewed on a high resolution touch screen display with graphics enhanced by the 2D and 3D graphics acceleration. The multi-standard video accelerator and an advanced audio subsystem are also included to provide advanced multimedia applications and services such as streaming audio and video, a multitude of decoders and encoders such as H. 264 and MPEG-4 Audio supports include FR HR, EFR, AMR FR, AMR HR and Wide-Band AMR vocoders, polyphonic ringtones and advanced audio functions such as echo cancellation, hands-free speakerphone operation and noise cancellation An ARMe Cortex-R4, DSP, and 2G and 3G coprocessors provide a powerful modem subsystem capable of supporting Category 24(42.2 Mbps) HSDPA downlink and Category 7(11.5 Mbps)HSUPA uplink data rates, as well as class 12 GPRS and EDGE Mediatek confidential @2012 Mediatek Inc Page 6 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A 1.1 Platform Features General Supports LPDDR2 up to 2GB Smartphone two MCU subsystems 32-bit data bus width architecture Memory clock up to 533MHZ SLC NAND flash and emmc bootloader Supports self-refresh/partial self-refresh mode · AP MCU subsystem Low-power operation Quad-core ARMe Cortex-A7 MPCore TM Programmable slew rate for memory ting at 1.2GHz ntroller’s| O pads NEoN multimedia processing engine Supports dual rank memory device with SIMDv2/FPv4 ISA support Advanced bandwidth arbitration control 32KB L1-cache and 32KB L1 D-cache 1 MB unified l2 cache Security DVFS technology with adaptive ARMO TrustZone Security operating voltage from 0.95V to 1.26V Connective MD MCU subsystem USB2.0 high-speed OTG supporting 15 ARM Cortex -R4 processor with TX and 15 Rx endpoints maximum 480MHz operation frequency USB2.0 full-speed host 64KB I-cache. 32KB D-cache NAND flash controller supporting NAND 256KB TCM(tightly-coupled memory) bootable. iNAND2R and moviNANDR DSP for running modem/voice tasks 4 UART for gPs. bt fm-rds. modem with maximum 240MHz operation and debugging interfaces frequency IrDA FIR/MIR/SIR High-performance AxI and AHB bus SPI for external device General dMA engine and dedicated 7 12C to control peripheral devices, e.g DMA channels for peripheral data CMOS image sensor, LCM or FM transfer er module Watchdog timer for system error 12S for connection with optional external ecovery hi-end audio codec Power management for clock gating GPIOs control 4 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC MD external interfaces and sDIo2.0/3.0 protocols Supports dual SIM/USIM interface Interface pins with RF and radio-related Operating conditions peripherals(antenna tuner, PA Core voltage: 1.05V UART for modem logging/debugging Processor DVFS voltage: 0.95V-126V urpose (Typ. 1.05V; sleep mode 0.85V Processor SRAM voltage: 1.05V External memory interface 1.26V(Typ. 1.05V; sleep mode 0.85V) Mediatek confidential @2012 Mediatek Inc Page 7 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A GPU voltage: 1.05V Type: FCCSP 10 voltage: 1.8V12.8V/3.3V 11.8mmx118mm Memory: 1.2V/1.8V/1.35V/1.5V/1.25V Height: 1.0mm maximur NAND: 1.8V/2.8V Ball count: 515 balls LCM interface: 1.8V Ball pitch: 0.4mm Clock source: 26MHz, 32,768kHz Package 1.2 MODEM Features 3G UMTS FDD supported features(with High dynamic range delta-sigma ADC MT6167) converts the downlink analog i and Q 3G modem supports most main teatures signals to digital baseband in 3GPP Release 7 and release 8 10-bit d/a converter for automatic CPC (DTX in CELL DCH, UL DRX DL Power Control(APC) DRX), HS-SCCH-less, HS-DSCH Programmable radio Rx filter with Dual cell operation adaptive gain control MAC-ehs Dedicated Rx filter for FB acquisition TWO DRX (receiver diversity)schemes Baseband Parallel Interface(BPl) with in ura PCh and cell Pch programmable driving strength(shared Uplink Cat. 7(16QAM), throughput up to by 2G& 3G modem) 11.5Mbps Supports multi-band Downlink Cat. 24(64QAM, dual-cell HSDPA), throughput up to 42 2Mbps GSM modem and voice codec Fast dormancy Dial tone generation ETWS Noise reduction Network selection enhancements Echo suppression Advanced sidetone oscillation reduction 3G TDD supported features(with Digital sidetone generator with MT6168 programmable gain TD-SCDMA/HSDPAHSUPa baseband Two programmable acoustic Supports tD-SCDMa Bands 34, 39& compensation filters 40 and Quad band GSM/EDGE GSM quad vocoders for adaptiV Circuit-switched voice and data. and multirate(AMR), enhanced full rate packet-switched data (EFR), full rate(FR)and half rate(HR) 384/384Kbps class in UL/DL for TD GSM channel coding, equalization and SCDMA A5/1, A5/2 and A5/3 ciphering TD-HSDPA: 2.8Mbps dl(cat. 14 GPRS GEA1GEA2 and gea3 TD-HSUPA: 2.2Mbps UL(Cat. 6) ciphering F8/F9 ciphering/integrity protection Programmable GSM/GPRS/EDGE odem Packet switched data with Radio interface and baseband front-end CS1/CS2/CS3/CS4 coding schemes Mediatek confidential @2012 Mediatek Inc Page 8 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A GSM circuit switch data GPRS/EdGE Class 12 Supports SAIC(single antenna interference cancellation) technology Supports VAMOs (Voice services over Adaptive Multi-user channels on One Slot technology in R9 spec 1.3 Multimedia Features Display Supports landscape or portrait panel Image resolution up to WXGA (1280X800 Integrated image signal processor Supports 8/9/16/18/24-bit host interface supports 13 MP up to 15fps (MIPI DBI) Supports electronic image stabilization Supports 8/9/16/24/32-bit serial Supports video stabilization interfaces Supports local contrast enhancement Supports 16/18/24-bit RGB interfaces Supports preference color adjustment (MIPI DPl) Supports noise reduction MIPI DSI interface(4 data lanes Supports multiple frame noise reduction Embedded LCd gamma correction for video recording Supports true colors Supports lens shading correction 4 overlay layers with per-pixel alpha Supports auto sensor detect pixel channel and gamma table correction Supports spatial and temporal dithering Supports AE/AWB/AF Supports side-by-side format output to Supports edge enhancement stereo 3d panel in both portrait and (sharpness) landscape modes Supports face detection and visual Supports external HDMI/MHL TX bridge tracking with 720p video output Supports multiple frame blending for Supports color enhancement multi-motion special effect Supports adaptive contrast Supports zero shutter delay image enhancement Supports image/video/graphic Supports capturing full size image when sharpness enhancement recording video(up to 8M sensor) Supports dynamic backlight scaling Supports capturing stereo image without bridge IC Graphics Supports stereo video recording without OpenGL ES 1.1/2.0 3d graphic bridge ic accelerator capable of processing 50M Supports MiPl CSl-2 high-speed tri/sec and 572M pixel/sec 286MHZ camera serial interface with 4 data lane (effective pixel rate: 1, 430M pixel/sec. (for main)+2 data lane(for stereo)+ 2 OpenvG1. 1 vector graphics accelerator data lane(for sub) 2D graphics hardware accelerator Supports Xenon flash Mediatek confidential @2012 Mediatek Inc Page 9 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited MT6589 MEDITEK HSPA+ Smartphone Application Processor Technical brief Confidential A Hardware jpeg decoder, Baseline Sample formats supported: 8-bit/16-bit, decoding with 42M pixel/sec, Mono/stereo progressive format decoding support Interfaces supported: DAL, 12S, PCM Hardware jPeg encoder: baseline 4-band lR compensation filter to encoding with 9oM pixel/sec enhance loudspeaker responses Supports YUV422/YUV420 color format Proprietary audio post-processing and eXiF/jfIF format technologies: BesLoudness, Android Hardware Webp decoder built-in post processing Audio encode: AMR-NB, AMR-WB. AAc · Video OGG H. 264 decoder: Baseline 1080p Audio decode: WAV MP3, MP2 30fps/40Mbps AAC, AMR-NB, AMR-WB MiDI Vorbis H. 264 decoder: Main/high profile APE, AAC-plus v1, AAC-plus v2, FLAC 1080p@30fps/40Mbps WMA Sorenson H 263/H263 decoder: 1080 30fps/40Mbps Speech MPEG-4 SP/ASP decoder: 1080p Speech codec(FR, HR, EFR, AMR FR, 30fps /40Mbps AMR HR and Wide-Band AMR) DIVX3/DIVX4/DIVX5/DIVX6/DIVX CTM HD/XVID decoder: 1080p@ Noise reduction 30fps/40Mbps Noise suppression VP8 decoder: 1080p 30fps/40Mbps Noise cancellation VC-1 decoder: 1080p@ 30fps/40Mbps Dual-Mic noise cancellation MPEG-4 encoder: Simple profile 1080p Echo cancellation 30fps Echo suppression H 263 encoder: 1080p 30fps Dual-MIC input H. 264 encoder: High profile 720p@ Digital MIC input 30fps P8 encoder: 720p@ 30tps · audio Sampling rates supported: 6kHz to 96kHz 1.4 General Descriptions MediaTek MT6589 is a highly integrated 3G System-on-chip Soc)which incorporates advanced features e.g. HSPA R8 modem, Quad-core ARM Cortex-A7 MPCore operating at 1.2 GHz, 3D graphics(OpenGLES 2.0), 13M camera ISP, LPDDR2 533MHz and high-definition 1080p video decoder. MT6589 helps phone manufacturers build high-performance 3G smart phones with PC-like browser, 3d gaming and cinema class home entertainment experiences World-leading technology Mediatek confidential @2012 Mediatek Inc Page 10 of 53 This document contains information that is proprietary to Mediatek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited

...展开详情
试读 53P MTK6589规格书
立即下载 低至0.43元/次 身份认证VIP会员低至7折
一个资源只可评论一次,评论内容不能少于5个字
您会向同学/朋友/同事推荐我们的CSDN下载吗?
谢谢参与!您的真实评价是我们改进的动力~
上传资源赚钱or赚积分
最新推荐
MTK6589规格书 9积分/C币 立即下载
1/53
MTK6589规格书第1页
MTK6589规格书第2页
MTK6589规格书第3页
MTK6589规格书第4页
MTK6589规格书第5页
MTK6589规格书第6页
MTK6589规格书第7页
MTK6589规格书第8页
MTK6589规格书第9页
MTK6589规格书第10页
MTK6589规格书第11页

试读结束, 可继续读5页

9积分/C币 立即下载