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IP178G 8 Port 10/100M Ethernet Integrated Switch
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IP178G
Data Sheet
1 / 77
February 05, 2013
Copyright © 2013, IC Plus Corp. IP178G-DS-R01.5.2
8 Port 10/100 Ethernet Integrated Switch
(85nm /Extreme Low Power, PWMT
®
and AFT
®
)
Features General Description
z 8 port Embedded 10/100 PHY Switch Controller
z Support 8 100BaseTX or 6 100Base TX + 2 FX
z 100M PHY support IEEE802.3az at full duplex
z 10M PHY only support 10BaseTe
z Support Auto MDI-MDIX function
z Power Management Tool (PWMT®)
- APS, auto-power saving while Link-off
- IEEE 802.3az protocol based power saving
- WOL+®, light traffic power saving
- PWD, force-off power saving
z Support Auto Factory Test (AFT®)
z Single Power 3.3V supply
z Built in 1.1V core voltage LDO Regulator
z Two Priority queues per port
z Support 802.1p & DiffServ based QoS
z QoS
- Port base
- 802.1p
- IP DiffServ IPV4/IPV6
- TCP/UDP port number
- Pins configure ports priority (VIP port)
z Support max forwarding packet length 1552/1536
bytes option
z Embedded 448K bits packet buffer
z Support port mirror function
z Support 1k MAC address
z Support broadcast storm protection
z Support port trunking (Link Aggregation)
z Support 16 VLAN (IEEE Std 802.1q)
- Port-based/Tagged-based VLAN
- Support Port-based insert, remove tag
z Built-in 50 ohm resistors for simplifying BOM
z 85nm Process
z Package and operation temperature
- IP178G: 68 Pin QFN, 0~70℃
IP178G is fabricated with advanced CMOS
(85nm) technology and only requires a 3.3V single
power supply. This feature makes IP178G used
very low power consume, such as the full load
operation (100Mbps full duplex 8 ports), it only
takes 0.95W.
IP178G also supports Power Management Tool
(PWMT
®) for IEEE 802.3az, APS, WOL+ and PWD
for Green Power. While two link devices have no
IEEE 802.3az capability, IP178G use WOL+ to
change link from 100Mbps to 10Mbps for saving
power.
The PWD, force-off power saving of IP178G is
designed for power down switch immediately by
pushing a button, user don’t plug out the power
adapter. Push the button again, it will power on
immediately.
Except Low Power and Rich Power Saving
method, IP178G supports AFT
® for saving
Customer Testing Cost. By using a push button and
cables, IP178G will Auto test completely by itself.
Application
8 port 10/100 Dumb switch
6TX+2FX Dumb Switch or 7TX + 1FX Dumb Switch
IP178G
Data Sheet
2 / 77
February 05, 2013
Copyright © 2013, IC Plus Corp. IP178G-DS-R01.5.2
Table of Contents
Features..................................................................................................................................................................................1
General Description...............................................................................................................................................................1
Table of Contents...................................................................................................................................................................2
List of Tables...........................................................................................................................................................................5
List of Figures.........................................................................................................................................................................6
Revision History.....................................................................................................................................................................7
Features comparison between IP178D and IP178G........................................................................................................8
1 Pin diagram....................................................................................................................................................................9
1.1 IP178G Pin diagram (QFN68)................................................................................................ 9
2 IP178G application diagram ......................................................................................................................................10
2.1 An 8 TP port switch application............................................................................................ 10
2.2 An 8-port switch mixed with two fiber ports ......................................................................... 10
2.3 TCP/UDP QoS Switch for time-sensitive application from EEPROM setting .......................11
2.4 Switch with VIP ports for specific users from Pin setting......................................................11
2.5 A 8-port Switch with Port mirror capability setting from EEPROM....................................... 12
3 Pin description.............................................................................................................................................................13
3.1 Analog pins .......................................................................................................................... 13
3.2 MDI (Media Dependent Interface) ....................................................................................... 13
3.3 System clock & reset pins.................................................................................................... 14
3.4 Boundry scan & test mode................................................................................................... 14
3.5 EEPROM interface /SMI (Serial Management interface) .................................................... 15
3.6 Frame priority setting pins.................................................................................................... 16
3.7 Miscellaneous setting pins................................................................................................... 17
3.8 LED interface ....................................................................................................................... 18
3.9 Power & ground pads .......................................................................................................... 18
4 Functional Description................................................................................................................................................19
4.1 Switch Engine and Queue Management ............................................................................. 19
4.1.1 Switch Engine ......................................................................................................... 19
4.1.2 Packet Forwarding.................................................................................................. 19
4.1.3 Flow control............................................................................................................. 19
4.1.4 Backpressure.......................................................................................................... 19
4.1.5 Broadcast storm protection..................................................................................... 19
4.2 Rserved Group MAC Address.............................................................................................. 20
4.3 Green Power........................................................................................................................ 21
4.3.1 Auto Power Saving Mode ....................................................................................... 21
4.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) ....................................................... 21
4.3.3 WOL+ (Wake On LAN Plus) ................................................................................... 21
4.3.4 Force Power Off...................................................................................................... 22
4.4 Auto Factory Test (AFT) Mode............................................................................................. 23
4.5 Reset.................................................................................................................................... 23
4.6 Serial management interface............................................................................................... 24
4.7 EEPROM interface............................................................................................................... 25
4.7.1 Example: Configure port based VLAN of IP178G .................................................. 25
4.8 CoS ...................................................................................................................................... 26
4.8.1 Port base priority..................................................................................................... 26
4.8.2 VIP ports ................................................................................................................. 26
4.8.3 Frame base priority................................................................................................. 27
4.8.3.1 VLAN tag and TCP/IP TOS........................................................................... 27
4.8.3.2 IPv4/IPv6 DiffServ......................................................................................... 28
4.8.3.3 TCP/UDP logical port priority ........................................................................ 29
4.9 Port Mirroring ....................................................................................................................... 29
4.10 Link Aggergation .................................................................................................................. 30
4.11 Buffer Aging.......................................................................................................................... 32
IP178G
Data Sheet
3 / 77
February 05, 2013
Copyright © 2013, IC Plus Corp. IP178G-DS-R01.5.2
4.12
LED display (normal operation) ........................................................................................... 32
4.13 Serial LED Mode.................................................................................................................. 32
4.13.1 Supports link LED only............................................................................................ 32
4.13.2 Supports link, speed, and duplex LED.................................................................... 33
4.14 LED Blink Timing.................................................................................................................. 33
4.15 PAD Driving Calibration ....................................................................................................... 34
4.16 Fiber port configuration........................................................................................................ 34
5 Register descriptions ..................................................................................................................................................35
5.1 Register map........................................................................................................................ 35
5.1.1 MII register map...................................................................................................... 35
6 PHY registers ..............................................................................................................................................................36
6.1 MII Register.......................................................................................................................... 37
6.2 MMD Control Register ......................................................................................................... 44
6.3 MMD Data Register ............................................................................................................. 45
6.4 LED mode Control Register................................................................................................. 48
6.5 WOL+ Control Register........................................................................................................ 49
6.6 Register Page mode Control Register................................................................................. 50
6.7 Switch control registers (I) ................................................................................................... 51
6.8 Test mode control registers.................................................................................................. 52
6.9 Port mirroring control registers............................................................................................. 53
6.10 Debug Regiister ................................................................................................................... 53
6.11 Fiber duplex setting registers............................................................................................... 54
6.12 Backpressure setting registers............................................................................................. 54
6.13 TCP/UDP port priority registers ........................................................................................... 55
6.14 Test mode............................................................................................................................. 55
6.15 CoS control registers – port 0 .............................................................................................. 56
6.16 CoS control registers – port 1 .............................................................................................. 56
6.17 CoS control registers – port 2 .............................................................................................. 56
6.18 CoS control registers – port 3 .............................................................................................. 56
6.19 CoS control registers – port 4 .............................................................................................. 57
6.20 CoS control registers – port 5 .............................................................................................. 57
6.21 CoS control registers – port 6 .............................................................................................. 57
6.22 CoS control registers – port 7 .............................................................................................. 57
6.23 Switch control registers (IV)................................................................................................. 58
6.24 Reserved Group MAC addresses........................................................................................ 59
6.25 Switch control registers (V).................................................................................................. 63
6.26 EEE Timing Parameter ........................................................................................................ 63
6.27 WOL (Wake on LAN)............................................................................................................ 64
6.28 Link Aggregation .................................................................................................................. 65
6.29 VLAN Group Control Register.............................................................................................. 65
6.29.1 VLAN Classification ................................................................................................ 65
6.29.2 VLAN Ingress Rule ................................................................................................. 66
6.29.3 Default VLAN Information ....................................................................................... 67
6.29.4 VLAN TAG Control Register ................................................................................... 67
6.29.5 Port Based VLAN Member Register....................................................................... 67
6.29.6 Leaky VLAN Control Register................................................................................. 68
6.30 VLAN Table .......................................................................................................................... 68
6.30.1 VLAN Control Register............................................................................................ 68
6.30.2 VLAN Identifier Register ......................................................................................... 68
6.30.3 VLAN Member Register.......................................................................................... 69
7 Electrical Characteristics ............................................................................................................................................71
7.1 Absolute Maximum Rating................................................................................................... 71
7.2 Crystal Specifications........................................................................................................... 71
7.3 DC Characteristic................................................................................................................. 71
7.3.1 Operating Conditions .............................................................................................. 71
IP178G
Data Sheet
4 / 77
February 05, 2013
Copyright © 2013, IC Plus Corp. IP178G-DS-R01.5.2
7.3.2
Input Clock .............................................................................................................. 71
7.3.3 I/O Electrical Characteristics................................................................................... 72
7.4 AC Timing............................................................................................................................. 72
7.4.1 Power On Sequence and Reset Timing.................................................................. 72
7.4.2 Serial Management Imierface Timing ..................................................................... 73
7.4.3 EEPROM Timing..................................................................................................... 74
7.4.3.1 Data read cycle ............................................................................................. 74
7.4.3.2 Command cycle ............................................................................................ 74
7.5 Thermal Data ....................................................................................................................... 74
8 Order Information........................................................................................................................................................75
9 Package Detail............................................................................................................................................................76
9.1 68 QFN Outline Dimensions ................................................................................................ 76
9.2 68 QFN PCB footprint.......................................................................................................... 77
IP178G
Data Sheet
5 / 77
February 05, 2013
Copyright © 2013, IC Plus Corp. IP178G-DS-R01.5.2
List of Tables
Table 1 IP178D and IP178G/GA Features comparison table..................................................... 8
Table 2 Pin description..............................................................................................................13
Table 3 Rserved Group MAC Address table.............................................................................20
Table 4 VIP port pin setting table.............................................................................................. 26
Table 5 TCP/UDP logical port priority table .............................................................................. 29
Table 6 LED Blink Timing.......................................................................................................... 33
Table 7 Fiber port Parameter.................................................................................................... 34
Table 8 MII register map table ..................................................................................................35
Table 9 PHY Register Map .......................................................................................................36
Table 10 MMD Control Register table....................................................................................... 44
Table 11 MMD Data Register table........................................................................................... 45
Table 12 LED mode Control Register table ..............................................................................48
Table 13 WOL+ Control Register table.....................................................................................49
Table 14 Page control registers table .......................................................................................50
Table 15 Switch control registers (I) table.................................................................................51
Table 16 Test mode control registers table...............................................................................52
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