JESD47I Stress-Test-Driven Qualification of Integrated Circuits

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Stress-Test-Driven Qualification of Integrated Circuits 2012JULY
PLEASE DONTⅤ IOLATE THE LAWI This document is copyrighted by JEDEC and may not be reproduced without permission For information contact JEDEC Solid State Technology Association 3103 North 1 Oth street Suite 240 South Arlington, VA 22201-2107 orrefertowww.jedec.orgunderStandards-documents/copyrightINformation JEDEC Standard No 47I P age STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS (From JEDEC Board Ballot, JCB-12-24, formulated under the cognizance of the JC143 Subcommittee on Silicon Devices Reliability Qualification and Monitoring) cope This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed These tests are capable of stimulating and precipitating semiconductor device and packaging failures The objective is to precipitate failures in an accelerated manner compared to use conditions. Failure rate projections usually require larger sample sizes than are called out in qualification testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs This qualification standard is aimed at a generic qualification for a range of use conditions, but is not applicable at extreme use conditions such as military applications, automotive under-the-hood applications, or uncontrolled avionics environments, nor does it address 2 level reliability considerations which are addressed in JEP150. where specific use conditions are established. qualification testin tailored to meet those specific requirements can be developed using jesd94 that will result in a better optimization of resources This set of tests should not be used indiscriminately. Each qualification project should be examined for a) Any potential new and unique failure mechanisms b) Any situations where these tests/conditions may induce invalid or overstress failures If it is known or suspected that failures either are due to new mechanisms or are uniquely induced by the severity of the test conditions, then the application of the test condition as stated is not recommended Alternatively, new mechanisms or uniquely problematic stress levels should be addressed by building an understanding of the mechanism and its behavior with respect to accelerated stress conditions(ref. JESD91, Method for developing acceleration Models for Electronic Component failure mechanisms and JESD94, "Application Specific Qualification using Knowledge Based Test Methodology") Consideration of pc board assembly-level effects may also be necessary. For guidance on this, refer to JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components This document does not relieve the supplier of the responsibility to assure that a product meets the complete set of its requirements JEDEC Standard No 47I Page 2 Reference documents The revision of the referenced documents shall be that which is in effect on the date of the qualification pl 2.1 Military MIL-STD-883, Test Methods and Procedures for Microelectronics MIL-PRF 38535 2.2 ndustrial UL94, Tests for Flammability of Plastic Materials for Parts in Devices and Appliances ASTM D2863, Flammability of Plastic Using the Oxygen Index Method IEC Publication 695, Fire lazard Testing J-STD-020, Joint IPC/JEDEC Standard, Moisture/Reflow Sensitivity Classification for Nonhermetic solid State Surface-Mount Devices JP-00l, Foundry Process Qualification Guidelines(Wafer Fabrication Manufacturing Sites) JESD22 Series, Reliabilily Test Methods or Packaged Devices JESD46, Guidelines for User Notification of Product/process Changes by Semiconductor Suppliers. JESD69, Information Requirements for the Qualification of silicon Devices JESD74, Early Life Failure Rate Calculation Procedure for Electronic Components JESD78, IC Latch-Up Test JESD85, Methods for Calculating Failure Rates in Units of FITs JESD86. Electrical Parameters Assessment JESD94, Application Specific Qualification using Knowledge Based Test Methodology JESD91, Methods for Developing Acceleration Models for Electronic Component Failure Mechanisms JEP122, Failure Mechanisms and Models for Semiconductor devices EP143, Solid State reliability Assessment qualification methodologies EP150, Stress-Test-Driven qualification of and Failure Mechanisms Associated with Assembled solid State surface-Mount Components JESD201, Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes JESD22A 121, Test Method for Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes JEDEC Standard No 47 Page 3 General requirements 3.1 Objective The objective of this procedure is to ensure that the device to be qualified meets a generally accepted set of stress test driven qualification requirements. Qualification is aimed at components used in commercial or industrial operating environments 3.2 Qualification family While this specification may be used to qualify an individual component, it is designed to also qualify a family of similar components utilizing the same fabrication process, design rules, and similar circuits The family qualification may also be applied to a package family where the construction is the same and only the size and number of leads differs. Interactive effects of the silicon and package shall be considered in applying family designations 3.3 Lot requirements Test samples shall comprise representative samples from the qualification family. Manufacturing variability and its impact on reliability shall be assessed. Where applicable the test samples will be means may be used to evaluate manufacturing variability. Sample size and pass/ fail requirements alo ate composed of approximately equal numbers from at least three (3 )nonconsecutive lots. Other appropri listed in Tables 1-3. Tables a and b give guidance on translating pass/fail requirements to larger sample Sizes Generic data and larger sample sizes may be employed based upon a Chi squared distribution using a total percent defective at a 90% confidence limit for the total required lot and sample size. ELFR requirements shall be assessed at a 60% confidence level as shown in Table B. If a single unique and expensive component is to be qualified, a reduced sample size qualification may be performed using 17/3 the sample size listed in the qualification tables 3.4 Production requirements All test samples shall be fabricated and assembled in the same production site and with the same production process for which the device and qualification family will be manufactured in production Samples need to be processed through the full production process including burn-in, handling, test, and screening. 3.5 Reusability of test samples Devices that have been used for nondestructive qualification tests may be used to populate other qualification tests. Devices that have been used in destructive qualification tests may not be used in subsequent qualification stresses except for engineering analysis. Non-destructive qualification tests are early Life Failure Rate, Electrical Parameters Assessment, External visual, System Soft error, and Physical dimensions JEDEC Standard no 47I Page 4 3.6 Definition of electrical test failure after stressil Post-stress electrical failures are defined as those devices not meeting the individual device specification or other criteria specific to the environmental stress If the cause of failure is due to causes unrelated to the test conditions the failure shall be discounted 3.7 Required stress tests for qualification Table 1, Table 2, and Table 3 list the qualification requirements for new components. Table 2 and Table 3 are differentiated by package type, but these are not exclusively packaging tests. Interactive effects of the packaging on the silicon also drive the need for tests in table 2 and Table 3. Power supply voltage for biased reliability stresses should be vcc max or v dd max as defined in the device datasheet as the maximum specified power supply operating voltage, usually the maximum power supply voltage is 5%to 10% higher than the nominal voltage. Some tests such as HTOL may allow for higher voltages to gain additional acceleration of stress time JEP122 can provide guidance for accelerating common failure mechanisms Table 4 lists the required stresses for a qualification family or category of change Interactive effects from the unchanged aspects of both the silicon and packaging must be assessed 3.8 Pass/Fail criteria Passing all appropriate qualification tests specified in Table 1, Table 2, and Table 3, either by performing the test, showing equivalent data with a larger sample size, or demonstrating acceptable generic data (using an equivalent total percent defective at a 90% confidence limit for the total required lot and sample size), qualifies the device per this document. When submitting test data from generic products or larger sample sizes to satisfy the Table l, table 2, and table 3 qualification requirements of this document, the number of samples and the total number of defective devices occurring during those tests must satisfy 90% confidence level of a Poisson exponential binomial distribution, as defined in MIL-PRF 38535 MIL-PRF 38535 is available for free from http://www.dscc.dlamil/prograMs/milspec/listdocs.asp?Basicdoc=mil-prF-38535.THeminimum number or samples for a given defect level can be approximated by the formula N>=0.5[X(2C+2,0.1)][1/LTPD-0.5]+C where c-accept N-Minimum Sample Size X is the Chi squared distribution value for a 90% CL and ltpd is the desired 90% confidence defect level. Table a is based upon this formula, but in some cases the sample sizes are slightly smaller than MIL-PRF-38535 JEDEC Standard No 47I Page 5 3.8 Pass/Fail criteria(contd) Table a- Sample Size for a Maximum Defective at a 90%Confidence Level EXAMPLE: USing generic data for HTOL with a requirement of o rejects from 230 samples. If 700 samples of generic data are available, the maximum number of failures that will meet the qualification test requirement is 3 failures from the ltPd-l column Qualification and requalification Qualification of a new device New or redesigned products(die revisions )manufactured in a currently qualified qualification family may be qualified using one(1) wafer/assembly lot. Electrical parameter assessment is one of the most Important tests to run 4.2 Requalification of a changed device Requalification of a device will be required when the supplier makes a change to the product and/or process that could potentially impact the form, fit, function, quality and/or reliability of the device. The guidelines for requalification tests required are listed in Table 4 4.2.1 Process change notification Supplier will meet the requirements of JESD46 Guidelines for User Notification of Product/Process Changes by Semiconductor Suppliers"for product/ process notification changes 4.2.2 Changes requiring requalification All product/process changes should be evaluated against the guidelines listed in Table 4 JEDEC Standard no 47I Page 6 4.2 Requalification of a changed device(contd 4.2.3 Criteria for passing requalification Table 4 lists qualification plan guidelines for performing the appropriate Table l, table 2, and table 3 stresses. Failed devices should be analyzed for root cause and correction; only a representative sample needs to be analyzed. Acceptable resolution of root cause and successful demonstration of corrective and preventive actions will constitute successful requalification of the device(s)affected by the change The part and or the qualification family can be qualified as long as containment of the problem is demonstrated until corrective and preventive actions are in place 5 Qualification tests 5.1 General tests st details are given in Table 1, Table 2, and Table 3. Not all tests apply to all devices table l tests generally apply to design and fabrication process changes. Table 2 tests are for non-hermetic packaged devices, and Table 3 is for hermetic packaged devices. Table B lists the pass/fail requirements for common infant mortality levels. Table 4 gives guidance as to which tests are required for a given process change. Some of the data required may be substituted by generic process or package data 5.2 Device specific tests The following tests must be performed on the specific device to be qualified for all hermetic and organic packages. Passing or failing these tests qualifies or disqualifies only the device under qualification and not the associated qualification family 1)Electrostatic Discharge(ESD)-All products-See table 2)Latch-up(Lu)-Required for CMOS, BiCMOS, and Bipolar technologies. See Table 1 3)Electrical Parameters Assessment-The supplier shall be capable of demonstrating, over the application temperature range, that the part is capable of meeting parametric limits in the individual device specification or data sheet 5.3 Wearout reliability tests Qualification family testing for the failure mechanisms listed below must be available upon request when a new wafer fabrication technology or a material relevant to the appropriate wearout failure mechanism is to be qualified. JP001 lists requirements for Fabrication Process Qualification. JEP 122 explains how to project wearout lifetime for these failure mechanisms. The following mechanisms need to be considered, but there may be other mechanisms to consider based upon technology details Electromigration; EM Time-Dependent Dielectric Breakdown; TDDB or Gate Oxide Integrity Test such as Charge to Breakdown Hot Carrier Injection: HcI Negative Bias Temperature Instability; NBT Stress Migration; SM, may be performed on an actual product The data, test method, calculations, and internal criteria need not be demonstrated or performed on the qualification of every new device

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