RK LINUX3.10-4.40 GMAC tx rx delay动态调整补丁V2.0.rar.rar

/******************************************************************************* This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. ST Ethernet IPs are built around a Synopsys IP Core. Copyright(C) 2007-2011 STMicroelectronics Ltd This program is free software; you can redistribute it and/or modify it under the terms and conditions of the GNU General Public License, version 2, as published by the Free Software Foundation. This program is distributed in the hope it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. The full GNU General Public License is included in this distribution in the file called "COPYING". Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> Documentation available at: http://www.stlinux.com Support available at: https://bugzilla.stlinux.com/ *******************************************************************************/ #include <linux/gpio.h> #include <linux/clk.h> #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/ip.h> #include <linux/tcp.h> #include <linux/skbuff.h> #include <linux/ethtool.h> #include <linux/if_ether.h> #include <linux/crc32.h> #include <linux/mii.h> #include <linux/if.h> #include <linux/if_vlan.h> #include <linux/dma-mapping.h> #include <linux/slab.h> #include <linux/prefetch.h> #ifdef CONFIG_GMAC_DEBUG_FS #include <linux/debugfs.h> #include <linux/seq_file.h> #endif /* CONFIG_GMAC_DEBUG_FS */ #include <linux/net_tstamp.h> #include "stmmac_ptp.h" #include "stmmac.h" #include "../eth_mac.h" #include <linux/regmap.h> #undef STMMAC_DEBUG /*#define STMMAC_DEBUG*/ #ifdef STMMAC_DEBUG #define DBG(nlevel, klevel, fmt, args...) \ ((void)(netif_msg_##nlevel(priv) && \ printk(KERN_##klevel fmt, ## args))) #else #define DBG(nlevel, klevel, fmt, args...) do { } while (0) #endif #undef STMMAC_RX_DEBUG /*#define STMMAC_RX_DEBUG*/ #ifdef STMMAC_RX_DEBUG #define RX_DBG(fmt, args...) printk(fmt, ## args) #else #define RX_DBG(fmt, args...) do { } while (0) #endif #undef STMMAC_XMIT_DEBUG /*#define STMMAC_XMIT_DEBUG*/ #ifdef STMMAC_XMIT_DEBUG #define TX_DBG(fmt, args...) printk(fmt, ## args) #else #define TX_DBG(fmt, args...) do { } while (0) #endif #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) #define JUMBO_LEN 9000 /* Module parameters */ #define TX_TIMEO 5000 static int watchdog = TX_TIMEO; module_param(watchdog, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); static int debug = -1; module_param(debug, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); int phyaddr = -1; module_param(phyaddr, int, S_IRUGO); MODULE_PARM_DESC(phyaddr, "Physical device address"); #define DMA_TX_SIZE 256 static int dma_txsize = DMA_TX_SIZE; module_param(dma_txsize, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); #define DMA_RX_SIZE 256 static int dma_rxsize = DMA_RX_SIZE; module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); static int flow_ctrl = FLOW_OFF; module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); static int pause = PAUSE_TIME; module_param(pause, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(pause, "Flow Control Pause Time"); #define TC_DEFAULT 64 static int tc = TC_DEFAULT; module_param(tc, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(tc, "DMA threshold control value"); #define DMA_BUFFER_SIZE BUF_SIZE_2KiB static int buf_sz = DMA_BUFFER_SIZE; module_param(buf_sz, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(buf_sz, "DMA buffer size"); static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); #define STMMAC_DEFAULT_LPI_TIMER 1000 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; module_param(eee_timer, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) /* By default the driver will use the ring mode to manage tx and rx descriptors * but passing this value so user can force to use the chain instead of the ring */ static unsigned int chain_mode; module_param(chain_mode, int, S_IRUGO); MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); static irqreturn_t stmmac_interrupt(int irq, void *dev_id); #ifdef CONFIG_GMAC_DEBUG_FS static int stmmac_init_fs(struct net_device *dev); static void stmmac_exit_fs(void); #endif #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) static int rkgmac_loopback_mode = 0; /** * stmmac_verify_args - verify the driver parameters. * Description: it verifies if some wrong parameter is passed to the driver. * Note that wrong parameters are replaced with the default values. */ static void stmmac_verify_args(void) { if (unlikely(watchdog < 0)) watchdog = TX_TIMEO; if (unlikely(dma_rxsize < 0)) dma_rxsize = DMA_RX_SIZE; if (unlikely(dma_txsize < 0)) dma_txsize = DMA_TX_SIZE; if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) buf_sz = DMA_BUFFER_SIZE; if (unlikely(flow_ctrl > 1)) flow_ctrl = FLOW_AUTO; else if (likely(flow_ctrl < 0)) flow_ctrl = FLOW_OFF; if (unlikely((pause < 0) || (pause > 0xffff))) pause = PAUSE_TIME; if (eee_timer < 0) eee_timer = STMMAC_DEFAULT_LPI_TIMER; } /** * stmmac_clk_csr_set - dynamically set the MDC clock * @priv: driver private structure * Description: this is to dynamically set the MDC clock according to the csr * clock input. * Note: * If a specific clk_csr value is passed from the platform * this means that the CSR Clock Range selection cannot be * changed at run-time and it is fixed (as reported in the driver * documentation). Viceversa the driver will try to set the MDC * clock dynamically according to the actual clock input. */ static void stmmac_clk_csr_set(struct stmmac_priv *priv) { u32 clk_rate; clk_rate = clk_get_rate(priv->stmmac_clk); /* Platform provided default clk_csr would be assumed valid * for all other cases except for the below mentioned ones. * For values higher than the IEEE 802.3 specified frequency * we can not estimate the proper divider as it is not known * the frequency of clk_csr_i. So we do not change the default * divider. */ if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { if (clk_rate < CSR_F_35M) priv->clk_csr = STMMAC_CSR_20_35M; else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) priv->clk_csr = STMMAC_CSR_35_60M; else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) priv->clk_csr = STMMAC_CSR_60_100M; else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) priv->clk_csr = STMMAC_CSR_100_150M; else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) priv->clk_csr = STMMAC_CSR_150_250M; else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; } } #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) static void print_pkt(unsigned char *buf, int len) { int j; pr_info("len = %d byte, buf addr: 0x%p", len, buf); for (j = 0; j < len; j++) { if ((j % 16) == 0) pr_info("\n %03x:", j); pr_info(" %02x", buf[j]); } pr_info("\n"); } #endif /* minimum number of free TX descriptors required to wake up TX process */ #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) { return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; } /** * stmmac_hw_fix_mac_speed: callback for speed selection