ENC28J60pdf

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MICROCHIP ENC28J60 Ethernet controller features Operational IEEE 802.3 compatible Ethernet controller Six interrupt sources and one interrupt output pin Integrated MAC and 1OBASE-TPhY 25 MHz clock input requirement Supports one 10BASE-T port with automatic Clock out pin with programmable prescaler polarity detection and correction Operating voltage of 3. 1V to 3.6V (3.3v typical) Supports Full and Half-Duplex modes 5V tolerant inputs Programmable automatic retransmit on collision Temperature range: -40C to +85C Industrial Programmable padding and Crc generation oC to +70C Commercial (SSoP only Programmable automatic rejection of erroneous 28-pin SPDIP, SSOP, SOIC, QFN packages packets SPI Interface with clock speeds up to 20 MHz Package Types Buffer 28-Pin SPDIP, SSOP, soIC 8-Kbyte transmit/receive packet dual port SRAM LEDA Configurable transmit/receive bufter size CLKOUT LEDB Hardware-managed circular receive fIFo INT VDDOSC NC 24日osc2 Byte-Wide random and sequential access with SO←6 OSC1 auto-increment 7 22凵 Vssosc Internal dma for fast data movement SCK 8 VssPLL 9 g VDDPLL Hardware assisted checksum calculation for vari 10 VDDRX ous network protocols 11 18口 VSSTX 12 TPOUT Medium Access Controller(MAC) TPIN+ 日13 16目→- TPOUT RBIAS 日14 15+VDDTX Features Supports Unicast, Multicast and Broadcast packets 28-pin QFN Programmable receive packet filtering and > wake-up host on logical and or or of the Unicast destination address 28272625242322 Multicast address 21口 VDDOSc Broadcast address 2 20口 Magic PacketT ENc28J6018 Group destination addresses as defined b 5 17 ∨s 64-bit hash table RESET 日6 16 VDDPLL Programmable pattern matching of up to VssRX 15口 VDDRX 64 bytes at user-defined offset 891011121314 凵口凵凵口凵 Physical Layer(PHY) Features Two programmable LED outputs for LINK, TX, RX, collision and full/half-duplex status Reserved pin; always leave disconnected o 2006 Microchip Technology Inc Preliminary DS39662B-page ENC28J60 Table of contents 0 Overvie 2.0 External Connections 3.0 Memory Organization 4.0 Serial Peripheral Interface(SPl) 25 5.0 Ethemet Overview 3 6.0 Initialization 7.0 Transmitting and Receiving Packets 8.0 Receive Filters 9.0 Duplex Mode Configuration and Negotiation 10.0 Flow Control 11.0 Reset 12.0 Interrupts 56777 …63 13.0 Direct Memory Access Controller 140 Power -Down 3 15.0 Built-in self-Test Controller 16.0 Electrical Characteristics 17.0 Packaging Information Index 89 The Microchip Web Site Customer Change Notification Service…… Customer Support... 9 Reader Response Product ldentification System TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip com or fax the Reader Response Form in the back of this data sheet to(480)792-4150 We welcome your feedback Most current data sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at http:/www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature number is the version number, (e.g, DS30000A is version A of document DS30000) Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device, please check with one of the following MicrochipsWorldwideWebsitehttp://www.microchip.com Your local Microchip sales office(see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number )you are Customer Notification System Registeronourwebsiteatwww.microchip.comtoreceivethemostcurrentinformationonallofour DS39662B-page 2 Preliminary C 2006 Microchip Technology Inc ENC28J60 10 OVERVIEW The ENC28J60 consists of seven major functional blocks The enc28J60 is a stand-alone ethernet controller with an industry standard Serial Peripheral Interface 1. An sp interface that serves as a communica- (SPI). It is designed to serve as an Ethernet network tion channel between the host controller and the interface for any controller equipped with SPl ENC28J60 2. Control Registers which are used to control and The ENc28J60 meets all of the ieEE 802.3 specifica monitor the enc28J60 tions. It incorporates a number of packet filtering schemes to limit incoming packets. It also provides an 3. a dual port RAM butter for received and internal DMA module for fast data throughput and hard transmitted data packets ware assisted checksum calculation which is used in 4. An arbiter to control the access to the ram various network protocols. Communication with the buffer when requests are made from dma host controller is implemented via an interrupt pin and transmit and receive blocks the SPl, with clock rates of up to 20 MHz. two dedi- 5. The bus interface that interprets data and cated pins are used for LEd link and network activity commands received via the spl interface indication 6. The MAC(Medium Access Control)module that a simple block diagram of the enc28J60 is shown in implements IEEE 802.3 compliant MAC logic Figure 1-1. a typical application circuit using the device 7. The Phy(Physical layer) module that encodes is shown in Figure 1-2. With the ENC28J60, two pulse and decodes the analog data that is present on transformers and a few passive components are all that the twisted pair interface is required to connect a microcontroller to an ethernet The device also contains other support blocks, such as network the oscillator, on-chip voltage regulator, level translators to provide 5v tolerant I/Os and system control logic FIGURE 1-1: ENC28J60 BLOCK DIAGRAM LEDA Buffer -区 LEDB 8 Kbytes Dual Port RAM MAC RXBM TPOUT+ RXF (Filter) cho Interface CLKOUT dMa Control Arbiter Checksum g Isters PHY TPIN- TXBM RXTPIN- 凶 Flow control Bus Interface MIIM RBIAS Interface Host Interface s(1) OSC1 Power-on Voltage 25 MHz OSC2 凶 System Control Reset Regulator Oscillator 凶 凶 VCAP Note 1: These pins are 5v tolerant 2006 Microchip Technology Inc Preliminary DS39662B-page 3 ENC28J60 FIGURE 1-2 TYPICAL ENC28J60-BASED INTERFACE MCU NC28J60 TPIN+ CS R.J45 TPOUT+/- SDO SDI ETHERNET SCK TX/RX PHY TRANSFORMER Buffer N LEDB TABLE 1-1 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin name SPDIP Description QFN Typ SOIC. SSOP VCAP 2.5V output from internal regulator. a low Equivalent Series Resistance (ESR)capacitor, with a typical value of 10 uF and a minimum value of 1 uF to ground, must be placed on this pin Vss 26 Ground reference CLKOUT INT NC SO 23456789 PO000 Programmable clock output pin (1) INT interrupt output pin. (2) Reserved function; always leave unconnected Data out pin for SPI interface. (2) ST Data in pin for SPl interface, (3) SCK sT Clock in pin for SPI interface.(3) ST Chip select input pin for SPI interface. (3, 4) RESET 10 ST Active-low device Reset input (3,4) VSSRX 23456789 Ground reference for Phy rX TPIN 12 ANa Differential signal input TPIN+ 13 ANA Differential signal input. RBIAS 10 ANA Bias current pin for PHY must be tied to ground via a resistor(refer to Section 2. 4 Magnetics, Termination and other External Components for details) VDDTX 15 11 Positive supply for PHY TX TPOUT 16 12 O Differential signal output TPOUT+ 13 ● Differential signal output VSSTX 14 Ground reference for Phy tx VDDRⅹ 15 Positive 3.3V supply for PHY RX DDPLL 16 Positive3V supply for PHY PLL. VSSPLL 21 Ground reference for PLL VSSOSc 22 18 Ground reference for oscillator 23 19 ANa Oscillator input 24 20 Oscillator output VDDOSC 25 21 Positive 3. 3V supply for oscillator LEDB LEDB driver pin(5) LEDA 27 o- LEDA driver pin(5) Positive 3. 3V supply. Legend: I=Input, O= Output, P 2A power, DIG-Digital input, ANA-Analog signal input, ST-Schmitt Trigger Note 1: Pins have a maximum current capacity of 8 mA 2: Pins have a maximum current capacity of 4 mA 3: Pins are 5v tolerant 4: Pins have an internal weak pull-up to VDD 5: Pins have a maximum current capacity of 12 mA DS39662B-page 4 Preliminary C 2006 Microchip Technology Inc ENC28J60 20 EXTERNAL CONNECTIONS 2.2 Oscillator Start-up Timer The ENC28J60 contains an Oscillator Start-up Timer 2.1 Oscillator (ost to ensure that the oscillator and integrated PHY The ENC28J60 is designed to operate at 25 MHz with have stabilized before use. The ost does not expire a crystal connected to the oSc1 and osc2 pins. The until 7500 OSC1 clock cycles (300 us) pass after ENc28J60 design requires the use of a parallel cut Power-on Reset or wake-up from Power-Down mode crystal. Use of a series cut crystal may give a frequency occurs. During the delay, all Ethernet registers and out of the crystal manufacturer specifications. a typical butter memory may still be read and written to through oscillator circuit is shown in Figure 2-1 the SPl bus. However, software should not attempt to transmit any packets(set ECON1.TXRTS), enable The ENC28J60 may also be driven by an external clock reception of packets(set ECoN1 RXEN or access any source connected to the OSC1 pin as shown in MAC, Mll or PHY registers during this period Figure 2-2 When the OST expires, the CLKRdy bit in the ESTAT FIGURE 2-1 CRYSTAL OSCILLATOR register will be set. The application software should poll OPERATION this bit as necessary to determine when normal device operation can begin FIGURE 2-2. EXTERNAL CLOCK SOURCE() O 2006 Microchip Technology Inc Preliminary DS39662B-page 5 ENC28J60 2.3 CLKOUT Pin value). Additionally, Power-Down mode may be entered and the clkout function will continue to The clock out pin is provided to the system designer for operate. When Power-Down mode is cancelled, the use as the host controller clock or as a clock source for ost will be reset but the clkout function will other devices in the system. The CLKoUT has an continue. When the clkout function is disabled internal prescaler which can divide the output by 1, 2 (ECOCON=0), the CLKoUT pin is driven lo 3. 4 8. The clkout function is enabled and the prescaler is selected via the ECoCoN register The ClKouT function is designed to ensure that mini- Register 2-1) mum timings are preserved when the CLKOUT pin function is enabled, disabled or the prescaler value is To create a clean clock signal, the CLKoUT pin is held changed. No high or low pulses will be outputted which low for a period when power is first applied. After the exceed the frequency specified by the ECOCON Power-on Reset ends, the OST will begin counting configuration. However, when switching frequencies, a When the OST expires, the ClKoUT pin will begin out- delay between two and eight OSC1 clock periods will putting its default frequency of 6.25 MHz(main clock occur where no clock pulses will be produced(see divided by 4). At any future time that the enc28J60 is Figure 2-3). During this period, CLKOUT will be held reset by software or the RESEt pin, the CLKoUT ful tion will not be altered(ECoCoN will not change FIGURE 2-3 CLKOUT TRANSITION ECOCON 80 ns to 320 ns delay REGISTER 2-1. ECOCON: CLOCK OUTPUT CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-1 R/W-0 RNW-0 COCON2 COCON1 COCONO bit 7 bit o egen R= Readable bit W=Writable bit U=Unimplemented bit, read as o n= value at POR 1= Bit is set 0= Bit is cleared x= Bit is unknown bit 7-3 Unimplemented Read as '0 bit 2-0 COCON2: COCONO: Clock Output Configuration bits 11x= Reserved for factory test. Do not use. Glitch prevention not assured 101=CLKOUT outputs main clock divided by 8 (3. 125 MHz) 100= CLKOUT outputs main clock divided by 4(6.25 MHz 011=CLKOUT outputs main clock divided by 3(8. 333333 MHz) 010= CLKOUT outputs main clock divided by 2(12.5 MHz) 001=CLKOUT outputs main clock divided by 1(25 MHz 000=CLKOUT is disabled. The pin is driven low DS39662B-page 6 Preliminary c 2006 Microchip Technology Inc ENC28J60 2.4 Magnetics, Termination and other a common-mode choke on the tpout interface External Components placed between the TPOUT pins and the Ethernet transformer (not shown), is not recommend. If a com To complete the Ethernet interface, the ENC28J60 mon-mode choke is used to reduce emi emissions it requires several standard components to be installed should be placed between the Ethernet transformer externally. These components should be connected as and pins 1 and 2 of the RJ-45 connector. Many Ether- shown in Figure 2-4 net transformer modules include common-mode The internal analog circuitry in the phy module requires chokes inside the same device package. The tran that an external 2.32 kQ2. 1% resistor be attached from formers should have at least the isolation rating speci RBIAS to ground. The resistor influences the TPOUT+/- fied in Table 16-5 to protect against static voltages and signal amplitude. The resistor should be placed as close meet IEEE 802.3 isolation requirements (see as possible to the chip with no immediately adjacent Section 160"Electrical Characteristics"for specifIc signal traces to prevent noise capacitively coupling into transformer requirements). Both transmit and receive the pin and affecting the transmit behavior. It is interfaces additionally require two resistors and a recommended that the resistor be a surface mount type capacitor to properly terminate the transmission line minimizing signal reflections Some of the device's digital logic operates at a nominal 2.5V. An on-chip voltage regulator is incorporated to All power supply pins must be externally connected generate this voltage. The only external component the same power source. Similarly, all ground refer- required is an external filter capacitor, connected from ences must be externally connected to the same VCAP to ground. The capacitor must have low equiva ground node. Each VDD and vss pin pair should have lent-series resistance(ESR), with a typical value of a 0. 1 uF ceramic bypass capacitor(not shown in the 10 uF, and a minimum value of 1 uF. The internal regu- schematic) placed as close to the pins as possible lator is not designed to drive external loads Since relatively high currents are necessary to operate On the TPIN+/TPIN-and TPOUT+/TPOUT- pins the twisted-pair interface, all wires should be kept as 1: 1 center-taped pulse transformers rated for Ethernet short as possible. Reasonable wire widths should be operations are required. When the Ethernet module is used on power wires to reduce resistive loss. If the enabled, current is continually sunk through both differential data lines cannot be kept short, they should TPOUT pins. When the PhY is actively transmitting, a be routed in such a way as to have a 100Q character differential voltage is created on the ethernet cable b istic impedance. varying the relative current sunk by TPOUT+ compared to tpout- FIGURE 2-4. ENC28J60 ETHERNET TERMINATION AND EXTERNAL CONNECTIONS ENC28J60 RJ-45 MCU TPOUT+ Ferrite vO 49.921%3Bad1,3 2 49941%千0.1pF TPOUT- 1:1CT 3 TPIN+ Level 4 Shift 49.99,1% 5 ≈4921%工01pF INTO INT IPIN 1:1CT 6 RBIAS 7 VCAP LEDA LEDE 8 2.32kg,1% 10 uF 759列75927592375g 1 nF.2 kv note 1: Ferrite bead should be rated for at least 80 mA 2: Required only if the microcontroller is operating at 5V. See Section 2. 5IO Levels"for more information 3: These components are installed for EMI reduction purposes O 2006 Microchip Technology Inc Preliminary DS39662B-page 7 ENC28J60 2.5 0 Levels 2.6 LED Configuration The ENC28J60 is a 3.3v part; however, it was The LEDa and LEdB pins support automatic polarity designed to be easily integrated into 5v systems. The detection on reset. the leds can be connected such SPI CS, sCK and SI inputs, as well as the reset pin that the pin must source current to turn the LEd on, or are all 5v tolerant. on the other hand. if the host alternately connected such that the pin must sink cur- controller is operated at 5V, it quite likely will not be rent to turn the LEd on. Upon system Reset, the within specifications when its SPl and interrupt inputs ENC28J60 will detect how the led is connected and are driven by the 3.3V CMOs outputs on the begin driving the LED to the default state configured by ENC28J60. A unidirectional level translator would be the PhLCon register. If the LEd polarity is changed necessary. while the ENC28J60 is operating the new polarity will An economical 74HCTo8 quad AND gate), 74ACT125 not be detected until the next system Reset occurs (quad 3-state buffer) or many other 5V CMOs chips LEDB is unique in that the connection of the LED is with TTL level input buffers may be used to provide the automatically read on Reset and determines how to ini- necessary level shifting. The use of 3-state buffers tialize the Phcon1. PDPXMd bit. If the pin sources permits easy integration into systems which share the current to illuminate the led, the bit is cleared on SPI bus with other devices. Figure 2-5 and Figure 2-6 Reset and the PhY defaults to half-duplex operation. If show example translation schemes the pin sinks current to illuminate the LED, the bit is set on Reset and the PhY defaults to full-duplex operation FIGURE 2-5: LEVEL SHIFTING USING Figure 2-7 shows the two available options if no LEd AND GATES is attached to the LEdB pin, the PdPXMd bit will reset to an indeterminate value MCU ENC28J60 FIGURE 2-7. LEDB POLARITY AND RESET CONFIGURATION OPTIONS SCK 凵scK SO Full-Duplex Operation ○+3.3V PDPXMD= 1 OSC1 CLKOUT LEDB INTO Half-Duplex Operation PDPXMD= O FIGURE 2-6 LEVEL SHIFTING USING EDB 3-STATE BUFFERS MCU ENC28J60 vO SCK SCK The LEds can also be configured separately to control their operating polarity(on or off when active), blink rate and blink stretch interval. The options are controlled by the lacFG3: LAcfgo and lBcFG3: LbcFgo bits LKOUT Typical values for blink stretch are listed in Table 2-1 INT TABLE 2-1: LED BLINK STRETCH LENGTH Stretch Length Typical Stretch(ms) TNSTRCH (normal) 40 TMSTRCH(medium) 70 TLSTRCH(long) 140 DS39662B-page 8 Preliminary c 2006 Microchip Technology Inc

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