STM32F103数据手册，144引脚LQFP封装。是103中比较全数据手册
Contents RMO008 5.2.2 Programmable voltage detector(PVD) 69 5.3 LoW-power modes 5.3.1 Slowing down system clocks 5.3.2 Peripheral clock gating ,,,,,72 5.3.3 Sleep mode 5.3.4 Stop mode 5.3.5 Standby mode 5.3.6 Auto-wakeup(AWU)from low-power mode 76 5.4 Power control registers 5.4. Power control register (PWR cr) ..,76 5. 4.2 Power control/status register (PWR_CSR) .78 54.3 PWR register map Backup registers(BKP)∴∴ 80 6.1 BKP introduction 80 6.2 BKP main features 80 6.3 BKP functional description 8 6.3. 1 Tamper detection 8 3.2 RTc calibration 6.4 BKP registers 82 4.1 Backup data register x(BKP_ DRx)(x=1. 42) 82 6.4.2 RTc clock calibration register(BKP_RTCCR) 82 6.4.3 Backup control register(BKP_CR) 6.4.4 Backup control 'status register(BKP_ CSr)...........83 6.4.5 BKP register map 84 7 LoW-, medium-, high-and XL-density reset and clock control(RCC) 89 7.1 Reset 89 7.1.1 System reset 7.1.2 Power reset 90 7.1.3 Backup domain reset Clocks 91 7.2. HSE Clock 93 7.2.2 HSI clock 94 7.2.3 PLL 5 3/1133 DocID13902 Rev 17 / RM0008 Contents 7.2.4 LSE clock 7.2.5 LSI clock 95 7.2.6 System clock (SYSCLk) selection 96 7. 2.7 Clock security system(CSS 7.2.8 RTc clock 97 7. 2. 9 Watchdog clock 97 7. 2. 10 Clock-out capability .,97 7.3 RCC registers 98 7.3.1 Clock control register (RCC_CR) 98 7.3.2 Clock configuration register(RCC CFGR) .100 7.3. 3 Clock interrupt register(RCC CIR) 103 7.3.4 APB2 peripheral reset register(RCC_ APB2RSTR) 105 7.3.5 APB1 peripheral reset register(RCC_APB1RSTR) 108 7.3.6 AHB peripheral clock enable register(RCC_AHBENR) 110 7.3.7 APB2 peripheral clock enable register(RCC_ APB2ENR) 111 7.3.8 APB1 peripheral clock enable register(RCC_ APB1ENR) ..114 7.3. 9 Backup domain control register(RCC_BDCR) 117 7.3. 10 Control/status register(RCC CSR) 118 7. 3.11 RCC register map 120 8 Connectivity line devices: reset and clock control (RCC)..... 122 8.1 Reset 122 8.1.1 System reset 122 8.1.2 Power reset 123 Backup domain reset ,,.124 8.2 Clocks 124 8.2.1 HSE clock 126 8.2.2 HSI clock 127 8.2.3 PLLS 128 8.2, 4 LSE clock ,,.128 8.2.5 LSI clock 129 8.2.6 System clock(SYSCLK) selection 129 827 Clock security systen(csS)..∴..,,…,.,…,130 8.2.8 RTC clock 130 8.2.9 Watchdog clock 130 8.2.10 Clock-out capability 131 8.3 RCC registers 13 DocID13902 Rev 17 4/1133 Contents RMO008 8.3.1 Clock control register(RCC Cr) 131 8.3.2 Clock configuration register(RCC_CFGR) 133 8.3.3 Clock interrupt register(RCC_ CIR) 136 8.3.4 APB2 peripheral reset register(RCC_APB2RSTR) 140 8.3.5 APB1 peripheral reset register(RCC_ APB1RSTR) 141 8.3.6 AHB Peripheral Clock enable register(RCC_AHBENR) ,,,144 8.3.7 AP B2 peripheral clock enable register(RCC_APB2ENR) .....145 8.3.8 APB1 peripheral clock enable register(RCC_ APB1ENR) 147 8.3.9 Backup domain control register(RCC_BDCr) .149 8.3.10 Control/status register(RCC_CSr) 151 8.3. 11 AHB peripheral clock reset register(RCC_AHBRSTR) 152 8.3. 12 Clock configuration register2 (RCC_CFGR2) 153 8.3.13 RCC register map 155 General-purpose and alternate function wos ( GPlOs and AFlOs)∴.…158 9.1 GPIO functional description .....158 9.1.1 General-purpose I0(GPlO) ,,.160 9.1.2 Atomic bit set or reset 160 9.1.3 External interrupt/wakeup lines 16 9.1.4 Alternate functions(AF) 161 9.1.5 Software remapping of /0 alternate functions 161 9.1.6 GPIO locking mechanism 9.1.7 Input contiguration 162 9.1.8 Output configuratio 162 9.1. 9 Alternate function configuration 163 9.1.10 Analog configuration .··: 164 9.1.11 GPIO configurations for device peripherals 165 9.2 GPIO registers 170 9.2.1 Port configuration register low(GPIOX_CRL)(X=A.G) ..170 9.2.2 Port configuration register high(GPIOX_CRH)(X=AG 171 9. 2. 3 Port input data register(GPIOX_IDR)(X=A G) ,,171 9. 2. 4 Port output data register (GPIOX_ODr)(=AG)........172 9.2.5 Port bit set/reset register(GPIOx BSRR)(X=A.G) ,,,.,,172 9.2.6 Port bit reset register(GPIOX BRR)(X=AG) .173 9.2.7 Port configuration lock register(GPIOx_LCKR)(x=AG).....173 9.3 Alternate function I/O and debug configuration(AFIO) 174 5/1133 DocID13902 Rev 17 / RM0008 Contents 9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 174 9.3.2 Using oSC_INOSC_OUT pins as GPIO ports PDO/PD1 174 9.33 CAN1 alternate function remapping 175 9.34 CAN2 alternate function remapping ....175 9.3. 5 JTAG/SWD alternate function remapping 175 9.3.6 ADC alternate function remapping 翻D 176 9.3.7 Timer alternate function remapping 177 9.3.8 USART alternate function remapping 179 9.3.9 12C1 alternate function remapping 180 9.3.10 SPI1 alternate function remapping 180 9.3.11 SPI3/12S3 alternate function remapping 9.3. 12 Ethernet alternate function remapping ..180 9. 4 AFIO registers 9.4.1 Event control register(AFIO_EVCR) 182 9. 4.2 AF remap and debug lo configuration register(AFIO_MAPR) 183 9. 4.3 External interrupt configuration register 1(AFIO_EXTICR1) 190 9.4.4 External interrupt configuration register 2(AFIO_EXTICR2 190 9.4.5 External interrupt configuration register 3(AFIO_ EXTICR3 .19 9.4.6 External interrupt configuration register 4(AFIO_EXTICR4)....191 9.4.7 AF remap and debug vo configuration register 2 (AFIO_ MAPR2).. 192 9.5 GPlO and aFlo register maps 193 10 Interrupts and events∴.∴.,, ■■■ 196 10.1 Nested vectored interrupt controller(NVIc) 96 10.1.1 Sys Tick calibration value register 196 10.1.2 Interrupt and exception vectors 197 10.2 External interrupt/event controller (EXTI) ,,,,206 10.2.1 Main features .206 10.2.2 Block diagram 206 10.2.3 Wakeup event management ,207 10.2.4 Functional descripti 207 10.2.5 EXternal interrupt/event line mapping 208 10.3 EXTI registers 210 10.3.1 Interrupt mask register(EXTI_IMR) ..210 10.3.2 Event mask register(EXTI_EMR) ,210 10.3.3 Rising trigger selection register(EXTI RTSR) 211 10.3. 4 Falling trigger selection register(EXTI_FTSR) 2 DocID13902 Rev 17 6/1133 Contents RMO008 10.3.5 Software interrupt event register (EXTISWIER) 212 10.3.6 Pending register(EXTI_PR 212 10.3.7 EXTI register map 213 Analog-to-digital converter(ADc) ■■■ ■■■ n,,,,,,214 11.1 ADC introduction 214 11.2 ADC main features 215 11.3 ADC functional description........... .,,,215 11.3.1 ADC on-off control 11.3.2 ADC clock 217 11.3.3 Channel selection 217 11.3.4 Single conversion mode 218 11.3.5 Continuous conversion mode 218 11.3.6 Timing diagram 218 11.3.7 Analog watchdog .219 11.3.8 Scan mode,,,,,,,, .220 3. 9 Injected channel management 220 11. 3.10 Discontinuous mode 221 11.4 Calibration.,,,,,,,,,,,,, 222 11.5 Data alignment 223 11.6 Channel-by-channel programmable sample time 224 11.7 Conversion on external trigger 224 11.8 DMa request 226 11.9 Dual adc mode n■ ,227 11.9.1 Injected simultaneous mode ...,.229 11.9.2 Regular simultaneous mode 229 11.9.3 Fast interleaved mode 230 11.9.4 Slow interleaved mode 230 11.9.5 Alternate trigger 11.9.6 Independent mode 232 11.9.7 Combined regular/injected simultaneous mode 232 11. 9.8 Combined regular simultaneous alternate trigger mode ,.,,,,232 11. 9.9 Combined injected simultaneous interleaved 23 11.10 Temperature sensor 234 11.11 ADC interrupts 235 11.12 ADC registers 236 7/1133 DocID13902 Rev 17 / RM0008 Contents 11.12.1 ADC status register (ADC_SR) 236 11.12.2 ADC control register 1(ADC_CR1) 237 11.12. 3 ADC control register 2(ADC_CR2) .239 11.12. 4 ADC sample time register 1(ADC_SMPR1) 243 11.12.5 ADC sample time register 2(ADC SMPR2 244 11.12.6 ADC injected channel data offset register x(ADC_ JOFRx)(x=1. 4).. 244 11.12.7 ADC watchdog high threshold register (ADC_HTR) ..,,.245 11.12.8 ADC watchdog low threshold register(ADC_LTR) 245 11.12.9 ADC regular sequence register 1(ADC_SQR1) 246 11.12. 10 ADC regular sequence register 2(ADC_SQR2) 247 11.12. 1 1 ADC regular sequence register 3(ADC_SQR3) 248 11.12. 12 ADC injected sequence register(ADC_JSQR) 249 11.12. 13 ADC injected data register x(ADC JDRX)(x= 1. 4) 250 11.12. 14 ADC regular data register(ADC_DR) 250 11.12.15 ADC register map 25 12 Digital-to-analog converter(DAC) m■ 253 12.1 DAC introduction 253 12.2 DAC main features 253 12. 3 DAC functional description 255 12.3.1 DAC channel enable 255 12.3.2 DAC output buffer enable ,,255 12.3.3 DAc data format 11■ .....255 12.3. 4 DAC conversion .256 12.3.5 DAC output voltage 257 12.3.6 DAC trigger selection 257 12.3.7 DMa request 258 12.3.8 Noise generation 258 12.3.9 Triangle-wave generation 259 12.4 Dual dac channel conversion ■■1■ 260 12.4.1 Independent trigger without wave generation 260 12.4.2 Independent trigger with same LF SR generation .26 12.4.3 Independent trigger with different LF SR generation .261 12.4.4 Independent trigger with same triangle generation 12.4.5 Independent trigger with different triangle generation 262 12.4.6 Simultaneous software start .262 12. 4.7 Simultaneous trigger without wave generation ,262 DocID13902 Rev 17 8/1133 Contents RMO008 12.4.8 Simultaneous trigger with same LFSR generation 263 12.4. 9 Simultaneous trigger with different LFSR generation 263 12.4.10 Simultaneous trigger with same triangle generation 263 12.4.11 Simultaneous trigger with different triangle generation 264 12.5 DAC registers 264 12.5.1 DAC control register(DAC_CR) 12.5.2 DAC software trigger register (DAC_SWTRIGR) 12.5.3 DAC channel1 12-bit right-aligned data holding register DAC DHR 12R1 268 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) 268 12.5.5 DAC channell 8-bit right aligned data g register (DAC_DHR8R1) 268 12.5.6 DAC channel2 12-bit right aligned data holding register DAC DHR12R2 269 2.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2 .269 12.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8 R2) 269 12.5.9 Dual DAC 12-bit right-aligned data holding register DAC_DHR12RD) 270 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) 270 12.5. 11 DUAL DAC 8-bit right aligned data holding register DAC_DHR8RD) 271 12.5. 12 DAC channel1 data output register(DAC_DOR1) 271 12.5. 13 DAC channel2 data output register(DAC_DOR2) 271 12.5.14 DAC register map 272 13 Direct memory access controller(DMA)........... 273 13.1 DMA introduction 273 13.2 DMA main features 273 13.3 DMA functional description ....275 13.3.1 DMa transactions 275 13.3.2 Arbiter 276 13.3.3 DMA channels 276 13.3.4 Programmable data width, data alignment and endians ..278 13.3.5 Error management 279 13.3.6 Interrupts ,,,,279 9/1133 DocID13902 Rev 17 / RM0008 Contents 13.3.7 DMA request mapping 280 13.4 DMA registers 283 13.4.1 DMA interrupt status register (DMA_ ISR) 283 13.4.2 DMA interrupt flag clear register(DMA_IFCR).................. 284 13.4.3 DMA channel x configuration register (DMA_ CCRx)(x=1.7, where x=channel number) 285 13.4. 4 DMA channel x number of data register(DMA- CNDTRx)(x=1.7. where x= channel number) ,,,,,,,,,,,,,,,,,,286 13.4.5 DMA channel x peripheral address register(DMA_CPARx)(x=1.7, where x=channel number) 287 13.4.6 DMA channel x memory address register(DMA_CMARX)(x=1.7 where x= channel number) .287 13.4.7 DMA register map 288 14 Advanced- control timers(TM1 and TIM8)∴∴ 291 14.1 tiM1 and tim introduction 29 14.2 TIM1 and tim main features 292 14.3 TIM1 and TIM8 functional description .294 14.3.1 Time-base unit 294 14.3.2 Counter modes ,,296 14.3.3 Repetition counter ......... 305 14.3.4 Clock selecti 307 14.3.5 Capture/compare channels .310 14.3.6 Input capture mode ,,,,,,313 14.3.7 PWM input mode 314 14.3.8 Forced output mode .315 14.3.9 Output compare mode 315 14.3. 10 PWM mode 14.3. 11 Complementary outputs and dead-time insertion 320 14.3.12 Using the break function 32 14.3.13 Clearing the OCXREF signal on an external event 325 14.3.14 6-step PWM generation .,326 14.3.15 One-pulse mode 327 14.3.16 Encoder interface mode 328 14.3.17 Timer input XOR function 331 14.3.18 Interfacing with Hall sensors 331 14.3.19 TIMx and external trigger synchronization 333 14.3.20 Timer synchronization ...336 DocID13902 Rev 17 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