全减器，用VHDL 自己编的
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2010-01-01
18:35:00
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LIBRARY IEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITY HALF_SUBER IS
PORT(A,B:IN STD_LOGIC;
S,CO:OUT STD_LOGIC);
END HALF_SUBER;
ARCHITECTURE HALF OF HALF_SUBER IS
COMPONENT HALF_SUBER
PORT(A,B:IN STD_LOGIC;
S,CO:OUT STD_LOGIC);
END COMPONENT;
BEGIN
S<='0' WHEN A='0' AND B='0' ELSE
'1' WHEN A='0' AND B='1' ELSE
'1' WHEN A='1' AND B='0' ELSE
'0' ;
CO<='0' WHEN A='0' AND B='0' ELSE
'1' WHEN A='0' AND B='1' ELSE
'0' WHEN A='1' AND B='0' ELSE
'0' ;
END HALF;
LIBRARY IEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITY FULL_SUBER IS
PORT(A,B,CIN:IN STD_LOGIC;
CO,S:OUT STD_LOGIC);
END FULL_SUBER;
ARCHITECTURE FULL OF FULL_SUBER IS
COMPONENT HALF_SUBER
PORT(A,B:IN STD_LOGIC;
S,CO:OUT STD_LOGIC);
END COMPONENT;
SIGNAL S1,S2,S3:STD_LOGIC;
BEGIN
U0:HALF_SUBER PORT MAP(A,B,S2,S1);
U1:HALF_SUBER PORT MAP(S2,CIN,S,S3);
CO<=S1 OR S3;
END FULL;
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