riscv-debug-spec-0.13 Riscv 调试V13

所需积分/C币:50 2019-02-27 09:20:15 747KB PDF
收藏 收藏
举报

riscv-debug-spec-0.13. riscv 调试协议 v13 版本,写的很详细,供参考
Preface Warning! This draft specification will change before being accepted as standard, so implementations made to this draft specification will likely not conform to the future standard Acknowledgments I would like to thank the following people for their time, feedback, and ideas: Bruce ablei- dinger, Krste Asanovic. Mark Beal, Alex Bradbury, Zhong-Ho Chen, Monte Dalrymple, Vyacheslav Dvanchenco, Peter Egold, Richard Herveille, Po-wei Huang, Scott Johnson, Aram Nahidipour Rishiyur Nikhil, Cajindcr Pancsar, Klaus Kruse Pcdcrscn, Antony Pavlov, Kcn Pcttit, Wesley Terpstra, Megan Wachs, Stefan Wallentowitz, Ray Van De Walker, Andrew Waterman, and Andy Wright RⅠSC-Ⅴ External Debug Support Version0.13 Contents Preface 1 Introduction 1.1 Terminology 1.1.1 Context 1.2 About This document 1.2.1 Structure 1.2.2 Register Definition Format 2 1.2.2. 1 Long Name(shortname, at Ox123 1.3 Background 1. 4 Supported Features 2 System overview 5 3 Debug Module(DM 3.1 Debug Module Interface(DMI) 3.2 Reset Control 3.3 Selecting Harts 3.3.1 Selecting a Single Hart 3.3.2 Selecting Multiple Harts 3.4 Run Control 3.5 Abstract commands RISC-V External Debug Support version 0.13 3.5.1 Abstract Command Listing 10 3.5.1.1 Access Register 3.5.1.2 Quick Access 2 3.6 Program Buffer .12 3.7 Overview of States 13 3.8 System Bus Access 3.9 Quick Access 15 3.10 Security 15 3.11 Debug Module DMI Registers 15 3.11.1 Debug Module Status(dmstatus, at Ox11 15 3. 11.2 Debug Module Control(decontrol, at 0x10 19 3.11.3 Hart Info(hartinfo, al 0x12 21 3.11.4 Halt Summary(haltsum, at 0x13) 22 3. 11.5 Hart Array Window Select(hawindowsel, at 0x14 .22 3.11.6 Hart Array Window(hawindow, at 0x15) 23 3. 11.7 Abstract Control and Status(abstracts, at 0x16) 23 3.11.8 Abstract Command (command, at 0x17) .24 3.11.9 Abstract Command Autoexec(abstractauto, at Ox18 26 3. 11.10 Device Tree Addr 0(devtreeaddrO, at Ox19 3. 11.11 Abstract Data 0(datao, at 0x04 27 3. 11.12 Program Buffer 0(progbufo, at 0x20) 27 3.11.13 Authentication Data(authdata, at 0x30) 27 3. 11.14 System Bus Access Control and Status(sbcs, at 0x38 27 3. 11.15 System Bus Address 31: 0(sbaddressO, at 0x39) 3. 11.16 System Bus Address 63: 32(sbaddress1, at 0x3a )0 3. 11. 17 System Bus Address 95: 64(sbaddress2, at 0x3b) 3. 11.18 System Bus Data 31: 0(sbdataO, at 0x3c 30 3.11.19 System Bus Data 63: 32(sbdatal, at Ox3d 31 RISC-V External Debug Support version 0.13 3.11.20 System Bus Data. 95: 64(sbdata2, at Ox3e 3. 11.21 System Bus Data 127: 96(sbdata3, at Ox3f 31 4 RISC-V Debug 33 4.1 Debug mode 33 4.2 Load-Reserved/ Store-Conditional Instructions 34 4.3 Singlc Stcp 34 4.4 Reset 34 4.4.1 dret Instruction 34 4.5 Core Debug registers 4.5.1 Debug Control and Status(dcsr, at 0x7b0 35 4.5.2 Dcbug PC(dpC, at Ox7b1) 37 4.5.3 Debug Scratch Register 0(dscratcho, at Ox7b2 4.5.4 Debug Scratch Register 1(dscratch1, at 0x7b3) 4.6 Virtual Debug Registers .38 4.6.1 Privilege Level (priv, at virtual) 38 5 Trigger Module 41 5.1 Trigger Registers 5.1.1 Trigger Select(select, at 0x7a0) 42 5.1.2 Trigger Data 1(tdatal, at Ox7a1) ,,42 5.1.3 Trigger Data 2(tdata2, at Ox7a2 43 5.1.4 Trigger Data 3(tdata3, at Ox7a3 5. 1.5 Match Control(control, at Ox7al 43 5.1.6 Instruction Count(icount, at Ox7al 47 6 Debug Transport Module (DTM) 49 6.1 JTAG Debug Transport module 6.1.1J① AG Background .49 RⅠSC-Ⅴ External Debug Support Version C.13 6.1.2 JTAG DTM Registers 6.1.3 IDCODE (at 0x01) 6.1.1 DTM Control and Status(dtmcs, at 0x10 51 6.1.5 Debug Module Interface Access(dmi, at 0x11) 52 6.1.6 BYPASS (at Ox1f) 54 6.1.7 Recommended JTAG Connector 54 a Hardware Implementations 57 A 1 Abstract Command bascd 57 A 2 Execution based 57 B Debugger Implementation 59 B. 1 Debug module interface access 59 B2 Main Loop 60 B 3 halting B 4 Running 60 B5 Single step B6 Accessing registers B.6. 1 Using abstract Command B.6.2 Using Program Buffer 61 B7 Reading Memory 61 B.7.1 Using System Bus Access 61 B.7.2 Using Program Buffer 62 B 8 Writing memory 63 B 8.1 Using System Bus Access 63 B 8.2 Using program buffer B9 Handling Exceptions 64 B 10 Quick Access 61 RISC-V External Debug Support version 0.13 C Future ideas 67 C 1 Serial Ports C.1.1 Serial Control and Status(sercs, at 0x34 C 1.2 Serial TX Data(sertx, at 0x35 C 1.3 Serial RX Data(serrx, at 0x36 69 Index 70 D Change Log 73 RⅠSC-Ⅴ External Debug Support Version0.13

...展开详情
试读 96P riscv-debug-spec-0.13 Riscv 调试V13
立即下载 低至0.43元/次 身份认证VIP会员低至7折
抢沙发
一个资源只可评论一次,评论内容不能少于5个字
  • GitHub

    绑定GitHub第三方账户获取
  • 至尊王者

    成功上传501个资源即可获取
关注 私信 TA的资源
上传资源赚积分or赚钱
最新推荐
riscv-debug-spec-0.13 Riscv 调试V13 50积分/C币 立即下载
1/96
riscv-debug-spec-0.13 Riscv 调试V13第1页
riscv-debug-spec-0.13 Riscv 调试V13第2页
riscv-debug-spec-0.13 Riscv 调试V13第3页
riscv-debug-spec-0.13 Riscv 调试V13第4页
riscv-debug-spec-0.13 Riscv 调试V13第5页
riscv-debug-spec-0.13 Riscv 调试V13第6页
riscv-debug-spec-0.13 Riscv 调试V13第7页
riscv-debug-spec-0.13 Riscv 调试V13第8页
riscv-debug-spec-0.13 Riscv 调试V13第9页
riscv-debug-spec-0.13 Riscv 调试V13第10页
riscv-debug-spec-0.13 Riscv 调试V13第11页
riscv-debug-spec-0.13 Riscv 调试V13第12页
riscv-debug-spec-0.13 Riscv 调试V13第13页
riscv-debug-spec-0.13 Riscv 调试V13第14页
riscv-debug-spec-0.13 Riscv 调试V13第15页
riscv-debug-spec-0.13 Riscv 调试V13第16页
riscv-debug-spec-0.13 Riscv 调试V13第17页
riscv-debug-spec-0.13 Riscv 调试V13第18页
riscv-debug-spec-0.13 Riscv 调试V13第19页
riscv-debug-spec-0.13 Riscv 调试V13第20页

试读结束, 可继续阅读

50积分/C币 立即下载 >