VERILOG实现的 超前进位加减法器
1星 需积分: 44 37 浏览量
2013-12-08
11:27:26
上传
评论
收藏 176KB ZIP 举报 
adsub4.zip （77个子文件） 
adsub4 
adsub4.fit.rpt 81KB adsub4.tan.rpt 10KB adsub4.qpf 1KB adsub4.eda.rpt 6KB adsub4.fit.summary 366B db adsub4.hier_info 2KB adsub4.tmw_info 364B adsub4.sld_design_entry.sci 168B adsub4.sgdiff.hdb 8KB adsub4.pre_map.cdb 2KB adsub4.tan.qmsg 6KB adsub4.tis_db_list.ddb 192B prev_cmp_adsub4.fit.qmsg 23KB adsub4.cmp.hdb 8KB adsub4.cmp0.ddb 20KB adsub4.lpc.rdb 548B adsub4.asm_labs.ddb 1008B adsub4.rpp.qmsg 2KB adsub4.db_info 151B adsub4.sld_design_entry_dsc.sci 168B adsub4.fit.qmsg 23KB
adsub4.lpc.txt 4KB adsub4.map.qmsg 5KB prev_cmp_adsub4.eda.qmsg 3KB adsub4.cbx.xml 88B adsub4.pre_map.hdb 8KB prev_cmp_adsub4.map.qmsg 5KB adsub4.cmp.cdb 4KB adsub4.syn_hier_info 0B adsub4.(0).cnf.hdb 859B adsub4.cmp.rdb 15KB
adsub4.lpc.html 5KB adsub4.map.logdb 4B adsub4.(2).cnf.cdb 726B adsub4.cmp.kpt 337B adsub4.(3).cnf.cdb 597B adsub4.sgdiff.cdb 1KB adsub4.map.hdb 8KB adsub4.rtlv.hdb 8KB prev_cmp_adsub4.asm.qmsg 2KB prev_cmp_adsub4.tan.qmsg 6KB adsub4.sgate.rvd 6KB adsub4.(1).cnf.cdb 2KB adsub4.(3).cnf.hdb 595B adsub4.eda.qmsg 3KB adsub4.hif 2KB adsub4.eco.cdb 175B adsub4.map.cdb 2KB adsub4.(2).cnf.hdb 651B adsub4.rtlv_sg_swap.cdb 938B adsub4.sgate_sm.rvd 229B adsub4.(1).cnf.hdb 1KB adsub4.rtlv_sg.cdb 3KB adsub4.cmp.tdb 3KB adsub4.cmp.logdb 4B prev_cmp_adsub4.qmsg 41KB adsub4.asm.qmsg 2KB adsub4.(0).cnf.cdb 1KB incremental_db compiled_partitions adsub4.root_partition.map.kpt 340B README 653B adsub4.map.rpt 26KB adsub4.qsf 3KB adsub4.pin 32KB adsub4.done 26B adsub4.v.bak 1KB adsub4.asm.rpt 6KB adsub4.map.summary 305B adsub4.tan.summary 712B simulation modelsim adsub4.sft 114B adsub4_modelsim.xrf 1KB adsub4_v.sdo 19KB adsub4.vo 22KB adsub4.pof 15KB adsub4.flow.rpt 8KB adsub4.qws 980B madsub4.v 828B adsub4.v 825B资源评论
JohnYork2019-03-25代码可用，但可读性不高，理解困难
hitblda2021-09-27不是我想要的。 也没可参考的内容，垃圾。
