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System Register index by encoding
</title><link rel="stylesheet" type="text/css" href="insn.css" /></head><body><table align="center"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Operations</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Operations</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td></tr></table><hr /><h1 class="sysregindex">System Register index by instruction and encoding</h1><p>Below are indexes for registers and operations accessed in the following ways:</p><p>For AArch32</p><ul><li><a href="#mrc_mcr_32">MRC/MCR</a></li><li><a href="#mrs_msr_32">MRS/MSR</a></li><li><a href="#vmrs_vmsr_32">VMRS/VMSR</a></li><li><a href="#mrrc_mcrr_32">MRRC/MCRR</a></li></ul><p>For AArch64</p><ul><li><a href="#mrs_msr_64">MRS/MSR</a></li><li><a href="#tlbi_64">TLBI</a></li><li><a href="#sysl_sys_64">SYSL/SYS</a></li><li><a href="#dc_ic_64">DC/IC</a></li><li><a href="#at_64">AT</a></li></ul><h2>Registers and operations in AArch32</h2>
<h2 class="sysregindex"><a name="mrc_mcr_32" id="mrc_mcr_32">
Accessed using MRC/MCR:
</a></h2><table class="instructiontable">
<thead>
<tr class="header1">
<th colspan="5">Register selectors</th>
<th rowspan="2">Name</th>
<th rowspan="2">Description</th>
</tr>
<tr class="header2">
<th class="bitfields">coproc</th>
<th class="bitfields">opc1</th>
<th class="bitfields">CRn</th>
<th class="bitfields">CRm</th>
<th class="bitfields">opc2</th>
</tr>
</thead>
<tbody>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0000</td>
<td class="bitfields">000</td>
<td>
<a href="AArch32-dbgdidr.html">DBGDIDR</a>
</td>
<td>Debug ID Register</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0000</td>
<td class="bitfields">010</td>
<td>
<a href="AArch32-dbgdtrrxext.html">DBGDTRRXext</a>
</td>
<td>Debug OS Lock Data Transfer Register, Receive, External View</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0001</td>
<td class="bitfields">000</td>
<td>
<a href="AArch32-dbgdscrint.html">DBGDSCRint</a>
</td>
<td>Debug Status and Control Register, Internal View</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0010</td>
<td class="bitfields">000</td>
<td>
<a href="AArch32-dbgdccint.html">DBGDCCINT</a>
</td>
<td>DCC Interrupt Enable Register</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0010</td>
<td class="bitfields">010</td>
<td>
<a href="AArch32-dbgdscrext.html">DBGDSCRext</a>
</td>
<td>Debug Status and Control Register, External View</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0011</td>
<td class="bitfields">010</td>
<td>
<a href="AArch32-dbgdtrtxext.html">DBGDTRTXext</a>
</td>
<td>Debug OS Lock Data Transfer Register, Transmit</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0101</td>
<td class="bitfields">000</td>
<td>
<a href="AArch32-dbgdtrrxint.html">DBGDTRRXint</a>
</td>
<td>Debug Data Transfer Register, Receive</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0101</td>
<td class="bitfields">000</td>
<td>
<a href="AArch32-dbgdtrtxint.html">DBGDTRTXint</a>
</td>
<td>Debug Data Transfer Register, Transmit</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0110</td>
<td class="bitfields">000</td>
<td>
<a href="AArch32-dbgwfar.html">DBGWFAR</a>
</td>
<td>Debug Watchpoint Fault Address Register</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0110</td>
<td class="bitfields">010</td>
<td>
<a href="AArch32-dbgoseccr.html">DBGOSECCR</a>
</td>
<td>Debug OS Lock Exception Catch Control Register</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">0111</td>
<td class="bitfields">000</td>
<td>
<a href="AArch32-dbgvcr.html">DBGVCR</a>
</td>
<td>Debug Vector Catch Register</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">xxxx</td>
<td class="bitfields">100</td>
<td>
<a href="AArch32-dbgbvrn.html">DBGBVR<n></a>
</td>
<td>Debug Breakpoint Value Registers</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">xxxx</td>
<td class="bitfields">101</td>
<td>
<a href="AArch32-dbgbcrn.html">DBGBCR<n></a>
</td>
<td>Debug Breakpoint Control Registers</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">xxxx</td>
<td class="bitfields">110</td>
<td>
<a href="AArch32-dbgwvrn.html">DBGWVR<n></a>
</td>
<td>Debug Watchpoint Value Registers</td>
</tr>
<tr>
<td class="bitfields">1110</td>
<td class="bitfields">000</td>
<td class="bitfields">0000</td>
<td class="bitfields">xxxx</td>
<td class="bitfields">1
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