PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0
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Contents
1. INTRODUCTION....................................................................................................................9
1.1. TERMS AND DEFINITIONS ..................................................................................................... 9
1.2. REFERENCE DOCUMENTS ................................................................................................... 10
1.3. SPECIFICATION CONTENTS.................................................................................................11
1.4. OBJECTIVES............................................................................................................................. 11
1.5. ELECTRICAL OVERVIEW .....................................................................................................12
1.6. MECHANICAL OVERVIEW ................................................................................................... 13
2. AUXILIARY SIGNALS........................................................................................................15
2.1. REFERENCE CLOCK...............................................................................................................16
2.1.1. Low Voltage Swing, Differential Clocks .................................................................... 16
2.1.2. Spread Spectrum Clocking (SSC)............................................................................... 17
2.1.3. REFCLK AC Specifications........................................................................................ 18
2.1.4. REFCLK Phase Jitter Specification For 2.5 GT/s Signaling Support ....................... 21
2.1.5. REFCLK Phase Jitter Specification For 5 GT/s Signaling Support ..........................22
2.2. PERST# SIGNAL ......................................................................................................................22
2.2.1. Initial Power-Up (G3 to S0).......................................................................................22
2.2.2. Power Management States (S0 to S3/S4 to S0).......................................................... 23
2.2.3. Power Down............................................................................................................... 24
2.3. WAKE# SIGNAL ......................................................................................................................26
2.4. SMBUS (OPTIONAL)............................................................................................................... 29
2.4.1. Capacitive Load of High-power SMBus Lines........................................................... 29
2.4.2. Minimum Current Sinking Requirements for SMBus Devices.................................... 30
2.4.3. SMBus “Back Powering” Considerations .................................................................30
2.4.4. Power-on Reset ..........................................................................................................30
2.5. JTAG PINS (OPTIONAL)......................................................................................................... 31
2.6. AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS................................................... 32
2.6.1. DC Specifications....................................................................................................... 32
2.6.2. AC Specifications ....................................................................................................... 33
3. HOT INSERTION AND REMOVAL..................................................................................35
3.1. SCOPE .................................................................................................................................... 35
3.2. PRESENCE DETECT................................................................................................................ 35
4. ELECTRICAL REQUIREMENTS .....................................................................................37
4.1. POWER SUPPLY REQUIREMENTS ......................................................................................37
4.2. POWER CONSUMPTION ........................................................................................................38
4.3. POWER SUPPLY SEQUENCING............................................................................................ 39
4.4. POWER SUPPLY DECOUPLING............................................................................................ 40
4.5. ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS .................................................... 40
4.5.1. Topologies.................................................................................................................. 40
4.5.2. Link Definition............................................................................................................ 42
4.6. ELECTRICAL BUDGETS ........................................................................................................43
4.6.1. AC Coupling Capacitors ............................................................................................ 44
4.6.2. Insertion Loss Values (Voltage Transfer Function)................................................... 44
4.6.3. Jitter Values................................................................................................................ 44
4.6.4. Crosstalk..................................................................................................................... 46
忧伤的石一2023-07-29文档中给出的测试规范严谨而实用，对于确保PCIE 2.0 CEM的可靠性和功能性非常有帮助。
whph2023-07-29总体而言，这份文件是一份资深工程师或相关领域专家必备的参考资料，对于确保测试结果的准确性和规范性有着积极的促进作用。
呆呆美要暴富2023-07-29该文件语言简洁明了，结构清晰，易于理解和操作。
玛卡库克2023-07-29文件内容准确可靠，提供了一系列经过验证的测试方法和标准，为PCIE 2.0 CEM的测试工作提供了坚实的指导。
焦虑肇事者2023-07-29这个文件详细而全面地介绍了PCIE 2.0 CEM 测试规范，对于需要了解或使用该规范的人来说是一份非常实用的资源。
