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-- Company:
-- Engineer:
--
-- Create Date: 18:23:32 11/24/2011
-- Design Name:
-- Module Name: yejing - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity yejing is
Port ( clk : in STD_LOGIC;
busy : in STD_LOGIC;
clr : in STD_LOGIC;
req : out STD_LOGIC;
cout : out STD_LOGIC;
dou : out STD_LOGIC_VECTOR (7 downto 0));
end yejing;
architecture Behavioral of yejing is
signal dout: std_logic_vector(7 downto 0);
signal q1 : std_logic_vector(30 downto 0);
signal c1,c2,oe : std_logic;
signal cou : integer range 0 to 2400;
signal count : integer range 0 to 16;
begin
process(clk)
begin
if(rising_edge(clk)) then
q1 <= q1 +1;
end if;
end process;
c1 <= q1(3);
c2 <= q1(15);
-- c3 <= q1(23);
process(busy,c1,clk)
begin
if(rising_edge(c1)) then
cout <= busy;
